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| Features * * * * * * * * Single Package Fully-integrated ROM Mask 4-bit Microcontroller with RF Transmitter Low Power Consumption in Sleep Mode (< 1 A Typically) Maximum Output Power with Low Supply Current 2.0V to 4.0V Operation Voltage for Single Li-cell Power Supply -40C to +125C Operation Temperature SSO24 Package About Seven External Components Flash Controller for Application Program Available 1. Description The ATAR862-4 is a single package triple-chip circuit. It combines a UHF ASK/FSK transmitter with a 4-bit microcontroller and a 512-bit EEPROM. It supports highly integrated solutions in car access and tire pressure monitoring applications, as well as manifold applications in the industrial and consumer segment. It is available for the transmitting frequency range of 429 MHz to 439 MHz with data rates up to 32 kbaud Manchester coded. For further frequency ranges such as 310 MHz to 330 MHz and 868 MHz to 928 MHz separate datasheets are available. The device contains a ROM mask version microcontroller and an additional data EEPROM. Figure 1-1. Application Diagram Microcontroller with UHF ASK/FSK Transmitter ATAR862-4 ATAR862-4 Antenna Keys Microcontroller PLLTransmitter UHF ASK/FSK Receiver Microcontroller 4552H-4BMCU-07/07 2. Pin Configuration Figure 2-1. Pinning SSO24 XTAL VS GND ENABLE NRESET BP63/T3I BP20/NTE BP23 BP41/T2I/VMI BP42/T2O BP43/SD/INT3 VSS 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 ANT1 ANT2 PA_ENABLE CLK BP60/T3O OSC2 OSC1 BP50/INT6 BP52/INT1 BP53/INT1 BP40/SC/INT3 VDD Table 2-1. Pin Pin Description: RF Part Symbol Function Configuration VS 1.5k 1.2k VS 1 XTAL Connection for crystal XTAL 182 A 2 3 VS GND Supply voltage Ground ESD protection circuitry (see Figure 7-5 on page 11) ESD protection circuitry (see Figure 7-5 on page 11) 4 ENABLE Enable input ENABLE 200k 2 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 Table 2-1. Pin Pin Description: RF Part (Continued) Symbol Function Configuration VS 21 CLK Clock output signal for microcontroller, the clock output frequency is set by the crystal to fXTAL/4 100 100 CLK PA_ENABLE 50k Uref = 1.1V 22 PA_ENABLE Switches on power amplifier, used for ASK modulation 20 A ANT1 23 24 ANT2 ANT1 Emitter of antenna output stage Open collector antenna output ANT2 Table 2-2. Name VDD VSS BP20 BP40 BP41 BP42 BP43 BP50 BP52 BP53 BP60 BP63 OSC1 OSC2 NRESET Pin Description: Microcontroller Part Type - - I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I O I/O Function Supply voltage Circuit ground Bi-directional I/O line of Port 2.0 Bi-directional I/O line of Port 4.0 Bi-directional I/O line of Port 4.1 Bi-directional I/O line of Port 4.2 Bi-directional I/O line of Port 4.3 Bi-directional I/O line of Port 5.0 Bi-directional I/O line of Port 5.2 Bi-directional I/O line of Port 5.3 Bi-directional I/O line of Port 6.0 Bi-directional I/O line of Port 6.3 Oscillator input Oscillator output Bi-directional reset pin Alternate Function - - NTE-test mode enable, see section "Master Reset" on page 23 SC-serial clock or INT3 external interrupt input VMI voltage monitor input or T2I external clock input Timer 2 T2O Timer 2 output SD serial data I/O or INT3-external interrupt input INT6 external interrupt input INT1 external interrupt input INT1 external interrupt input T3O Timer 3 output T3I Timer 3 input 4-MHz crystal input or 32-kHz crystal input or external clock input or external trimming resistor input 4-MHz crystal output or 32-kHz crystal output or external clock input - Pin No. 13 12 7 14 9 10 11 17 16 15 20 6 18 19 5 Reset State NA NA Input Input Input Input Input Input Input Input Input Input Input Input I/O 3 4552H-4BMCU-07/07 3. UHF ASK/FSK Transmitter Block 4. Features * Integrated PLL Loop Filter * Maximum Output Power (10 dBm) with Low Supply Current (9.5 mA Typically) * Modulation Scheme ASK/FSK - FSK Modulation is Achieved by Connecting an Additional Capacitor between the XTAL Load Capacitor and the Open-drain Output of the Modulating Microcontroller Easy to Design-in Due to Excellent Isolation of the PLL from the PA and Power Supply Supply Voltage 2.0V to 4.0V in the Temperature Range of -40C to +125C Single-ended Antenna Output with High Efficient Power Amplifier External CLK Output for Clocking the Microcontroller 125C Operation for Tire Pressure Systems * * * * * 5. Description The PLL transmitter block has been developed for the demands of RF low-cost transmission systems, at data rates up to 32 kbaud. The transmitting frequency range is 429 MHz to 439 MHz. It can be used in both FSK and ASK systems. 4 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 Figure 5-1. Block Diagram ATAR862-4 Power up/ down CLK f 4 f 32 ENABLE PFD VS PA_ENABLE GND CP ANT2 LF ANT1 PA PLL VCO XTO XTAL OSC2 OSC1 V DD V SS Microcontroller NRESET Brown-out protect. RESET Voltage monitor External input VMI BP10 Port 1 BP13 BP20/NTE Data direction RC Crystal oscillators oscillators External clock input UTCM Timer 1 interval- and watchdog timer Timer 2 T2I T2O SD Clock management ROM 4 K x 8 bit RAM 256 x 4 bit 8-/12-bit timer with modulator SSI Serial interface SC T3O T3I 4-bit CPU core I/O bus Timer 3 8-bit timer/counter with modulator and demodulator BP22 BP23 Port 2 BP21 Data direction + alternate function Port 4 Data direction + interrupt control Port 5 Data direction + alternate function Port 6 EEPROM 32 x 16 bit BP51 INT6 BP40 BP41 BP42 BP43 BP50 INT3 VMI T2O INT3 INT6 SC T2I SD BP52 BP53 INT1 INT1 BP60 T3O BP63 T3I 5 4552H-4BMCU-07/07 6. General Description The fully-integrated PLL transmitter that allows particularly simple, low-cost RF miniature transmitters to be assembled. The VCO is locked to 32 x fXTAL, thus, a 13.56 MHz crystal is needed for a 433.92 MHz transmitter. All other PLL and VCO peripheral elements are integrated. The XTO is a series resonance oscillator so that only one capacitor together with a crystal connected in series to GND are needed as external elements. The crystal oscillator together with the PLL needs maximum < 1 ms until the PLL is locked and the CLK output is stable. A wait time of 1 ms until the CLK is used for the microcontroller and the PA is switched on. The power amplifier is an open-collector output delivering a current pulse which is nearly independent from the load impedance. The delivered output power is controlled via the connected load impedance. This output configuration enables a simple matching to any kind of antenna or to 50. A high power efficiency of = Pout/(IS,PA x VS) of 36% for the power amplifier results when an optimized load impedance of ZLoad = (166 + j223) is used at 3V supply voltage. 7. Functional Description If ENABLE = L and PA_ENABLE = L, the circuit is in standby mode consuming only a very small amount of current so that a lithium cell used as power supply can work for several years. With ENABLE = H, the XTO, PLL and the CLK driver are switched on. If PA_ENABLE remains L, only the PLL and the XTO are running and the CLK signal is delivered to the microcontroller. The VCO locks to 32 times the XTO frequency. With ENABLE = H and PA_ENABLE = H, the PLL, XTO, CLK driver and the power amplifier are on. With PA_ENABLE, the power amplifier can be switched on and off, which is used to perform the ASK modulation. 7.1 ASK Transmission The PLL transmitter block is activated by ENABLE = H. PA_ENABLE must remain L for t 1 ms, then the CLK signal can be taken to clock the microcontroller and the output power can be modulated by means of pin PA_ENABLE. After transmission, PA_ENABLE is switched to L and the microcontroller switches back to internal clocking. The PLL transmitter block is switched back to standby mode with ENABLE = L. 7.2 FSK Transmission The PLL transmitter block is activated by ENABLE = H. PA_ENABLE must remain L for t 1 ms, then the CLK signal can be taken to clock the microcontroller and the power amplifier is switched on with PA_ENABLE = H. The chip is then ready for FSK modulation. The microcontroller starts to switch on and off the capacitor between the XTAL load capacitor and GND with an open-drain output port, thus changing the reference frequency of the PLL. If the switch is closed, the output frequency is lower than if the switch is open. After transmission PA_ENABLE is switched to L and the microcontroller switches back to internal clocking. The PLL transmitter block is switched back to standby mode with ENABLE = L. The accuracy of the frequency deviation with XTAL pulling method is about 25% when the following tolerances are considered. 6 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 Figure 7-1. Tolerances of Frequency Modulation ~ VS CStray1 XTAL CStray2 CM LM C0 Crystal equivalent circuit RS C4 C5 CSwitch Using C4 = 9.2 pF 2%, C5 = 6.8 pF 5%, a switch port with CSwitch = 3 pF 10%, stray capacitances on each side of the crystal of CStray1 = CStray2 = 1 pF 10%, a parallel capacitance of the crystal of C0 = 3.2 pF 10% and a crystal with CM = 13 fF 10%, an FSK deviation of 21 kHz typical with worst case tolerances of 16.3 kHz to 28.8 kHz results. ~ 7.3 CLK Output An output CLK signal is provided for a connected microcontroller. The delivered signal is CMOS compatible if the load capacitance is lower than 10 pF. 7.3.1 Clock Pulse Take Over The clock of the crystal oscillator can be used for clocking the microcontroller. The microcontroller block has the special feature of starting with an integrated RC-oscillator to switch on the PLL transmitter block with ENABLE = H, and after 1 ms to assume the clock signal of the transmission IC, so the message can be sent with crystal accuracy. Output Matching and Power Setting The output power is set by the load impedance of the antenna. The maximum output power is achieved with a load impedance of ZLoad,opt = (166 + j223). There must be a low resistive path to VS to deliver the DC current. The delivered current pulse of the power amplifier is 9 mA and the maximum output power is delivered to a resistive load of 465 if the 1.0 pF output capacitance of the power amplifier is compensated by the load impedance. An optimum load impedance of: ZLoad = 465 || j/(2 x 1.0 pF) = (166 + j223) thus results for the maximum output power of 7.5 dBm. The load impedance is defined as the impedance seen from the PLL transmitter block's ANT1, ANT2 into the matching network. Do not confuse this large signal load impedance with a small signal input impedance delivered as input characteristic of RF amplifiers and measured from the application into the IC instead of from the IC into the application for a power amplifier. Less output power is achieved by lowering the real parallel part of 465 where the parallel imaginary part should be kept constant. Output power measurement can be done with the circuit shown in Figure 7-2 on page 8. Note that the component values must be changed to compensate the individual board parasitics until the PLL transmitter block has the right load impedance ZLoad,opt = (166 + j223). Also the damping of the cable used to measure the output power must be calibrated. 7.3.2 7 4552H-4BMCU-07/07 Figure 7-2. Output Power Measurement VS C1 = 1n L1 = 33n ANT1 ZLopt ANT2 ~ C2 = 2.2p Power meter Z = 50 R in 50 7.4 Application Circuit For the supply-voltage blocking capacitor C3, a value of 68 nF/X7R is recommended (see Figure 7-3 on page 9 and Figure 7-4 on page 10). C1 and C2 are used to match the loop antenna to the power amplifier where C1 typically is 8.2 pF/NP0 and C2 is 6 pF/NP0 (10 pF + 15 pF in series); for C2 two capacitors in series should be used to achieve a better tolerance value and to have the possibility to realize the ZLoad,opt by using standard valued capacitors. C1 forms together with the pins of PLL transmitter block and the PCB board wires a series resonance loop that suppresses the 1st harmonic, thus, the position of C1 on the PCB is important. Normally the best suppression is achieved when C1 is placed as close as possible to the pins ANT1 and ANT2. The loop antenna should not exceed a width of 1.5 mm, otherwise the Q-factor of the loop antenna is too high. L1 (50 nH to 100 nH) can be printed on PCB. C4 should be selected so the XTO runs on the load resonance frequency of the crystal. Normally, a value of 12 pF results for a 15 pF load-capacitance crystal. 8 ATAR862-4 4552H-4BMCU-07/07 ~ ATAR862-4 Figure 7-3. ASK Application Circuit VS L1 C4 XTAL 1 XTAL XTO VCO PA 24 ANT1 C1 VS VS 2 CP C3 23 ANT2 LF C2 Loop Antenna GND 3 PFD 22 PA_ENABLE 32 PLL f 4 f Power up/down 21 CLK ENABLE 4 NRESET 5 BP63/T3I 6 BP20/NTE 7 BP23 8 BP41/T2I/VMI 9 BP42/T2O 10 BP43/SD/ INT3 BP60/T3O 20 OSC2 19 OSC1 18 BP50/INT6 S1 17 BP52/INT1 S2 16 BP53/INT1 S3 15 BP40/SC/INT3 17 VDD 13 11 VSS 12 VS 9 4552H-4BMCU-07/07 Figure 7-4. FSK Application Circuit VS L1 C4 XTAL 1 C5 XTAL XTO VCO PA 24 ANT1 C1 VS VS 2 CP C3 23 ANT2 LF C2 Loop Antenna GND 3 PFD 22 PA_ENABLE 32 PLL f 4 f Power up/down 21 CLK ENABLE 4 NRESET 5 BP63/T3I 6 BP20/NTE 7 BP23 8 BP41/T2I/VMI 9 BP42/T2O 10 BP43/SD/ INT3 BP60/T3O 20 OSC2 19 OSC1 18 BP50/INT6 S1 17 BP52/INT1 S2 16 BP53/INT1 S3 15 BP40/SC/INT3 17 VDD 13 11 VSS 12 VS 10 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 Figure 7-5. ESD Protection Circuit VS ANT1 CLK PA_ENABLE ANT2 XTAL ENABLE GND 8. Absolute Maximum Ratings: RF Part Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Supply voltage Power dissipation Junction temperature Storage temperature Ambient temperature Input voltage Note: Symbol VS Ptot Tj Tstg Tamb VmaxPA_ENABLE -55 -55 -0.3 Min. Max. 5 100 150 +125 +125 (VS + 0.3) (1) Unit V mW C C C V 1. If VS + 0.3 is higher than 3.7V, the maximum voltage will be reduced to 3.7V. 9. Thermal Resistance Parameters Junction ambient Symbol RthJA Value 135 Unit K/W 10. Electrical Characteristics VS = 2.0V to 4.0V, Tamb = -40C to +125C unless otherwise specified. Typical values are given at VS = 3.0V and Tamb = 25C. All parameters are referred to GND (Pin 3). Parameters Test Conditions Power down, VENABLE < 0.25V, -40C to +85C VPA-ENABLE < 0.25V, -85C to +125C VPA-ENABLE < 0.25V, +25C (100% correlation tested) Power up, PA off, VS = 3V VENABLE > 1.7V, VPA-ENABLE < 0.25V Power up, VS = 3.0V VENABLE > 1.7V, VPA-ENABLE > 1.7V VS = 3.0V, Tamb = 25C f = 433.92 MHz, ZLoad = (166 + j233) Symbol Min. Typ. Max. 350 7 < 10 Unit nA A nA Supply current IS_Off Supply current Supply current Output power IS IS_Transmit PRef 5.5 3.7 9 7.5 4.8 11.6 10 mA mA dBm 11 4552H-4BMCU-07/07 10. Electrical Characteristics (Continued) VS = 2.0V to 4.0V, Tamb = -40C to +125C unless otherwise specified. Typical values are given at VS = 3.0V and Tamb = 25C. All parameters are referred to GND (Pin 3). Parameters Output power variation for the full temperature range Test Conditions Tamb = -40C to +85C VS = 3.0V VS = 2.0V Tamb = -40C to +125C VS = 3.0V VS = 2.0V POut = PRef + PRef Selectable by load impedance fCLK = f0/128 Load capacitance at pin CLK = 10 pF fO 1 x fCLK fO 4 x fCLK other spurious are lower fXTO = f0/32 fXTAL = resonant frequency of the XTAL, CM 10 fF, load capacitance selected accordingly Tamb = -40C to +85C Tamb = -40C to +125C Referred to fPC = fXT0, 25 kHz distance to carrier 25 kHz distance to carrier at 1 MHz at 36 MHz fVCO 429 f0/128 CLoad 10 pF V0h V0l Rs Duty cycle of the modulation signal = 50% Duty cycle of the modulation signal = 50% Low level input voltage High level input voltage Input current high Low level input voltage High level input voltage Input current high VIl VIh IIn VIl VIh IIn VS x 0.8 VS x 0.2 110 7 0 0 32 32 0.25 1.7 20 1.7 0.25 VS(1) 5 Symbol PRef PRef PRef PRef POut_typ 0 Min. Typ. Max. -1.5 -4.0 -2.0 -4.5 7.5 Unit dB dB dB dB dBm Output power variation for the full temperature range Achievable output-power range Spurious emission -55 -52 dBc dBc Oscillator frequency XTO (= phase comparator frequency) fXTO -30 -40 fXTAL 250 -116 -86 -94 -125 -110 -80 -90 -121 439 +30 +40 ppm ppm kHz dBc/Hz dBc/Hz dBc/Hz dBc/Hz MHz MHz V V pF kHz kHz V V A V V A PLL loop bandwidth Phase noise of phase comparator In loop phase noise PLL Phase noise VCO Frequency range of VCO Clock output frequency (CMOS microcontroller compatible) Voltage swing at pin CLK Series resonance R of the crystal Capacitive load at pin XT0 FSK modulation frequency rate ASK modulation frequency rate ENABLE input PA_ENABLE input Note: 1. If VS is higher than 3.6V, the maximum voltage will be reduced to 3.6V. 12 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 11. Microcontroller Block 12. Features * * * * * Extended Temperature Range for High Temperature up to 125C 4-Kbyte ROM, 256 x 4-bit RAM 11 Bi-directional I/Os Up to Seven External/Internal Interrupt Sources Multifunction Timer/Counter - IR Remote Control Carrier Generator - Biphase-, Manchester- and Pulse-width Modulator and Demodulator - Phase Control Function Programmable System Clock with Prescaler and Five Different Clock Sources Supply-voltage Range (2.0V to 4.0V) Very Low Sleep Current (< 1 A) 32 x 16-bit EEPROM Synchronous Serial Interface (2-wire, 3-wire) Watchdog, POR and Brown-out Function Voltage Monitoring Inclusive Lo_BAT Detect Flash Controller ATAM862 Available (SSO24) * * * * * * * * 13. Description The ATAR862-4 is a member of Atmel's family of 4-bit single-chip microcontrollers. The ATAR862-4 is suitable for the transmitter side as well as the receiver side. It contains ROM, RAM, parallel I/O ports, two 8-bit programmable multifunction timer/counters with modulator and demodulator function, voltage supervisor, interval timer with watchdog function and a sophisticated on-chip clock generation with external clock input, integrated RC-oscillator, 32-kHz and 4-MHz crystal-oscillators. The ATAR862-4 has an EEPROM as a third chip in one package. 13 4552H-4BMCU-07/07 Figure 13-1. Block Diagram V SS V DD OSC1 OSC2 Brown-out protect. RESET Voltage monitor External input VMI BP10 Port 1 BP13 BP20/NTE RC Crystal oscillators oscillators External clock input UTCM Timer 1 interval- and watchdog timer Timer 2 T2I T2O SD Clock management ROM 4 K x 8 bit RAM 256 x 4 bit 8/12-bit timer with modulator SSI MARC4 Data direction Port 2 Serial interface Timer 3 8-bit timer / counter with modulator and demodulator SC T3O T3I BP21 BP22 BP23 4-bit CPU core I/O bus Data direction + alternate function Port 4 Data direction + interrupt control Port 5 Data direction + alternate function Port 6 BP52 BP50 BP40 BP42 INT1 INT3 T2O INT6 BP53 BP51 SC BP41 BP43 INT3 INT6 INT1 VMI T2I SD BP60 T3O BP63 T3I 14. Introduction The ATAR862-4 is a member of Atmel's family of 4-bit single-chip microcontrollers. It contains ROM, RAM, parallel I/O ports, two 8-bit programmable multifunction timer/counters, voltage supervisor, interval timer with watchdog function and a sophisticated on-chip clock generation with integrated RC-, 32-kHz and 4-MHz crystal oscillators. Table 14-1. Version Flash device Production Available Variants Type ATAM862 ATAR862 ROM 4-Kbyte EEPROM 4-Kbyte Mask ROM E2PROM Peripheral 64-bytes 64-bytes Packages SSO24 SSO24 14 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 15. MARC4 Architecture General Description The MARC4 microcontroller consists of an advanced stack-based, 4-bit CPU core and on-chip peripherals. The CPU is based on the Harvard architecture with physically separated program memory (ROM) and data memory (RAM). Three independent buses, the instruction bus, the memory bus and the I/O bus, are used for parallel communication between ROM, RAM and peripherals. This enhances program execution speed by allowing both instruction prefetching, and a simultaneous communication to the on-chip peripheral circuitry. The extremely powerful integrated interrupt controller with associated eight prioritized interrupt levels supports fast and efficient processing of hardware events. The MARC4 is designed for the high-level programming language qFORTH. The core includes both an expression and a return stack. This architecture enables high-level language programming without any loss of efficiency or code density. Figure 15-1. MARC4 Core MARC4 CORE Reset Program memory PC X Y SP RP RAM 256 x 4-bit Reset Clock Instruction bus Instruction decoder Memory bus TOS CCR System clock Sleep Interrupt controller I/O bus ALU On-chip peripheral modules 16. Components of MARC4 Core The core contains ROM, RAM, ALU, program counter, RAM address registers, instruction decoder and interrupt controller. The following sections describe each functional block in more detail. 15 4552H-4BMCU-07/07 16.1 ROM The program memory (ROM) is mask programmed with the customer application program during the fabrication of the microcontroller. The ROM is addressed by a 12-bit wide program counter, thus predefining a maximum program bank size of 4 Kbytes. An additional 1-Kbyte of ROM exists, which is reserved for quality control self-test software The lowest user ROM address segment is taken up by a 512-bytes Zero page which contains predefined start addresses for interrupt service routines and special subroutines accessible with single byte instructions (SCALL). The corresponding memory map is shown in Figure 16-1. Look-up tables of constants can also be held in ROM and are accessed via the MARC4's built-in table instruction. Figure 16-1. ROM Map of the Microcontroller Block FFFh 1F8h 1F0h 1E8h 1E0h 1E0h 1C0h 180h INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 SCALL addresses ROM (4 K x 8 bit) 7FFh Zero page 140h 1 00h 0C0h 0 80h 1FFh Zero page 000h 020h 018h 010h 008h 000h 040h 008h 0 00h $RESET $AUTOSLEEP 16.2 RAM The microcontroller block contains 256 x 4-bit wide static random access memory (RAM), which is used for the expression stack. The return stack and data memory are used for variables and arrays. The RAM is addressed by any of the four 8-bit wide RAM address registers SP, RP, X and Y. 16.2.1 Expression Stack The 4-bit wide expression stack is addressed with the expression stack pointer (SP). All arithmetic, I/O and memory reference operations take their operands, and return their results to the expression stack. The MARC4 performs the operations with the top of stack items (TOS and TOS-1). The TOS register contains the top element of the expression stack and works in the same way as an accumulator. This stack is also used for passing parameters between subroutines and as a scratch pad area for temporary storage of data. Return Stack The 12-bit wide return stack is addressed by the return stack pointer (RP). It is used for storing return addresses of subroutines, interrupt routines and for keeping loop index counts. The return stack can also be used as a temporary storage area. The MARC4 instruction set supports the exchange of data between the top elements of the expression stack and the return stack. The two stacks within the RAM have a user definable location and maximum depth. 16.2.2 16 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 Figure 16-2. RAM Map RAM (256 x 4-bit) Autosleep FCh FFh Global variables Expression stack 3 0 TOS TOS-1 TOS-2 4-bit Expression stack Return stack SP RAM address register: X Y Return stack 11 0 RP SP TOS-1 RP 04h 00h 07h 03h Global v variables 12-bit 16.3 Registers The microcontroller has seven programmable registers and one condition code register (see Figure 16-3). 16.3.1 Program Counter (PC) The program counter is a 12-bit register which contains the address of the next instruction to be fetched from the ROM. Instructions currently being executed are decoded in the instruction decoder to determine the internal micro-operations. For linear code (no calls or branches), the program counter is incremented with every instruction cycle. If a branch-, call-, return-instruction or an interrupt is executed, the program counter is loaded with a new address. The program counter is also used with the table instruction to fetch 8-bit wide ROM constants. Figure 16-3. Programming Mode l 11 PC 7 RP 7 SP 7 X 7 Y 3 TOS 3 C -B 0 I 0 Top of stack register Condition code register Interrupt enable Branch Reserved Carry / borrow 0 RAM address register (Y) 0 RAM address register (X) 0 0 0 0 Expression stack pointer Return stack pointer 0 Program counter CCR 17 4552H-4BMCU-07/07 16.3.2 RAM Address Registers The RAM is addressed with the four 8-bit wide RAM address registers: SP, RP, X and Y. These registers allow access to any of the 256 RAM nibbles. Expression Stack Pointer (SP) The stack pointer contains the address of the next-to-top 4-bit item (TOS-1) of the expression stack. The pointer is automatically pre-incremented if a nibble is moved onto the stack or post-decremented if a nibble is removed from the stack. Every post-decrement operation moves the item (TOS-1) to the TOS register before the SP is decremented. After a reset, the stack pointer has to be initialized with >SP S0 to allocate the start address of the expression stack area. Return Stack Pointer (RP) The return stack pointer points to the top element of the 12-bit wide return stack. The pointer automatically pre-increments if an element is moved onto the stack, or it post-decrements if an element is removed from the stack. The return stack pointer increments and decrements in steps of 4. This means that every time a 12-bit element is stacked, a 4-bit RAM location is left unwritten. This location is used by the qFORTH compiler to allocate 4-bit variables. After a reset the return stack pointer has to be initialized via >RP FCh. RAM Address Registers (X and Y) The X and Y registers are used to address any 4-bit item in the RAM. A fetch operation moves the addressed nibble onto the TOS. A store operation moves the TOS to the addressed RAM location. By using either the pre-increment or post-decrement addressing mode arrays in the RAM can be compared, filled or moved. Top of Stack (TOS) The top of stack register is the accumulator of the MARC4. All arithmetic/logic, memory reference and I/O operations use this register. The TOS register receives data from the ALU, ROM, RAM or I/O bus. Condition Code Register (CCR) The 4-bit wide condition code register contains the branch, the carry and the interrupt enable flag. These bits indicate the current state of the CPU. The CCR flags are set or reset by ALU operations. The instructions SET_BCF, TOG_BF, CCR! and DI allow direct manipulation of the condition code register. Carry/Borrow (C) The carry/borrow flag indicates that the borrowing or carrying out of arithmetic logic unit (ALU) occurred during the last arithmetic operation. During shift and rotate operations, this bit is used as a fifth bit. Boolean operations have no effect on the C-flag. Branch (B) The branch flag controls the conditional program branching. Should the branch flag has been set by a previous instruction, a conditional branch will cause a jump. This flag is affected by arithmetic, logic, shift, and rotate operations. 16.3.3 16.3.4 16.3.5 16.3.6 16.3.7 16.3.8 16.3.9 18 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 16.3.10 Interrupt Enable (I) The interrupt enable flag globally enables or disables the triggering of all interrupt routines with the exception of the non-maskable reset. After a reset or while executing the DI instruction, the interrupt enable flag is reset, thus disabling all interrupts. The core will not accept any further interrupt requests until the interrupt enable flag has been set again by either executing an EI or SLEEP instruction. 16.4 ALU The 4-bit ALU performs all the arithmetic, logical, shift and rotate operations with the top two elements of the expression stack (TOS and TOS-1) and returns the result to the TOS. The ALU operations affects the carry/borrow and branch flag in the condition code register (CCR). Figure 16-4. ALU Zero-address Operations RAM SP TOS-1 TOS-2 TOS-3 TOS-4 ALU CCR TOS 16.5 I/O Bus The I/O ports and the registers of the peripheral modules are I/O mapped. All communication between the core and the on-chip peripherals take place via the I/O bus and the associated I/O control. With the MARC4 IN and OUT instructions, the I/O bus allows a direct read or write access to one of the 16 primary I/O addresses. More about the I/O access to the on-chip peripherals is described in the section "Peripheral Modules" on page 32. The I/O bus is internal and is not accessible by the customer on the final microcontroller device, but it is used as the interface for the MARC4 emulation (see section "Emulation" on page 105). 16.6 Instruction Set The MARC4 instruction set is optimized for the high level programming language qFORTH. Many MARC4 instructions are qFORTH words. This enables the compiler to generate a fast and compact program code. The CPU has an instruction pipeline allowing the controller to prefetch an instruction from ROM at the same time as the present instruction is being executed. The MARC4 is a zero-address machine, the instructions contain only the operation to be performed and no source or destination address fields. The operations are implicitly performed on the data placed on the stack. There are one- and two-byte instructions which are executed within 1 to 4 machine cycles. A MARC4 machine cycle is made up of two system clock cycles (SYSCL). Most of the instructions are only one byte long and are executed in a single machine cycle. For more information refer to the "MARC4 Programmer's Guide". 19 4552H-4BMCU-07/07 16.7 Interrupt Structure The MARC4 can handle interrupts with eight different priority levels. They can be generated from the internal and external interrupt sources or by a software interrupt from the CPU itself. Each interrupt level has a hard-wired priority and an associated vector for the service routine in the ROM (see Table 16-1 on page 21). The programmer can postpone the processing of interrupts by resetting the interrupt enable flag (I) in the CCR. An interrupt occurrence will still be registered, but the interrupt routine only started after the I-flag is set. All interrupts can be masked, and the priority individually software configured by programming the appropriate control register of the interrupting module (see section "Peripheral Modules" on page 32). 16.7.1 Interrupt Processing For processing the eight interrupt levels, the MARC4 includes an interrupt controller with two 8-bit wide interrupt pending and interrupt active registers. The interrupt controller samples all interrupt requests during every non-I/O instruction cycle and latches these in the interrupt pending register. If no higher priority interrupt is present in the interrupt active register, it signals the CPU to interrupt the current program execution. If the interrupt enable bit is set, the processor enters an interrupt acknowledge cycle. During this cycle a short call (SCALL) instruction to the service routine is executed and the current PC is saved on the return stack. An interrupt service routine is completed with the RTI instruction. This instruction resets the corresponding bits in the interrupt pending/active register and fetches the return address from the return stack to the program counter. When the interrupt enable flag is reset (triggering of interrupt routines is disabled), the execution of new interrupt service routines is inhibited but not the logging of the interrupt requests in the interrupt pending register. The execution of the interrupt is delayed until the interrupt enable flag is set again. Note that interrupts are only lost if an interrupt request occurs while the corresponding bit in the pending register is still set (i.e., the interrupt service routine is not yet finished). It should be noted that automatic stacking of the RBR is not carried out by the hardware and so if ROM banking is used, the RBR must be stacked on the expression stack by the application program and restored before the RTI. After a master reset (power-on, brown-out or watchdog reset), the interrupt enable flag and the interrupt pending and interrupt active register are all reset. 16.7.2 Interrupt Latency The interrupt latency is the time from the occurrence of the interrupt to the interrupt service routine being activated. This is extremely short (taking between 3 to 5 machine cycles depending on the state of the core). 20 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 Figure 16-5. Interrupt Handling INT7 7 6 5 INT5 INT7 active RTI Priority Level INT5 active 4 3 2 1 0 INT3 INT2 INT3 active RTI RTI INT2 pending INT2 active RTI SWI0 INT0 pending INT0 active RTI Main / Autosleep Main / Autosleep Time Table 16-1. Interrupt INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7 Interrupt Priority Table Priority Lowest | | | | | | Highest ROM Address 040h 080h 0C0h 100h 140h 180h 1C0h 1E0h Interrupt Opcode C8h (SCALL 040h) D0h (SCALL 080h) D8h (SCALL 0C0h) E8h (SCALL 100h) E8h (SCALL 140h) F0h (SCALL 180h) F8h (SCALL 1C0h) FCh (SCALL 1E0h) Function Software interrupt (SWI0) External hardware interrupt, any edge at BP52 or BP53 Timer 1 interrupt SSI interrupt or external hardware interrupt at BP40 or BP43 Timer 2 interrupt Timer 3 interrupt External hardware interrupt, at any edge at BP50 or BP51 Voltage monitor (VM) interrupt 21 4552H-4BMCU-07/07 Table 16-2. Hardware Interrupts Interrupt Mask Interrupt INT1 INT2 INT3 INT4 INT5 Register P5CR T1M SISC T2CM T3CM1 T3CM2 T3C P5CR VCM Bit P52M1, P52M2 P53M1, P53M2 T1IM SIM T2IM T3IM1 T3IM2 T3EIM P50M1, P50M2 P51M1, P51M2 VIM Interrupt Source Any edge at BP52 any edge at BP53 Timer 1 SSI buffer full/empty or BP40/BP43 interrupt Timer 2 compare match/overflow Timer 3 compare register 1 match Timer 3 compare register 2 match Timer 3 edge event occurs (T3I) Any edge at BP50, any edge at BP51 External/internal voltage monitoring INT6 INT7 16.8 Software Interrupts The programmer can generate interrupts by using the software interrupt instruction (SWI), which is supported in qFORTH by predefined macros named SWI0...SWI7. The software triggered interrupt operates exactly like any hardware triggered interrupt. The SWI instruction takes the top two elements from the expression stack and writes the corresponding bits via the I/O bus to the interrupt pending register. Therefore, by using the SWI instruction, interrupts can be re-prioritized or lower priority processes scheduled for later execution. 16.9 Hardware Interrupts In the microcontroller block, there are eleven hardware interrupt sources with seven different levels. Each s ource can be masked individua lly by m ask bits in the c orre spo ndin g control registers. An overview of the possible hardware configurations is shown in Table 16-2. 22 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 17. Master Reset The master reset forces the CPU into a well-defined condition. It is unmaskable and is activated independent of the current program state. It can be triggered by either initial supply power-up, a short collapse of the power supply, brown-out detection circuitry, watchdog time-out, or an external input clock supervisor stage (see Figure 17-1). A master reset activation will reset the interrupt enable flag, the interrupt pending register and the interrupt active register. During the power-on reset phase, the I/O bus control signals are set to reset mode, thereby, initializing all on-chip peripherals. All bi-directional ports are set to input mode. Attention: During any reset phase, the BP20/NTE input is driven towards VDD by an additional internal strong pull-up transistor. This pin must not be pulled down to VSS during reset by any external circuitry representing a resistor of less than 150 k. Releasing the reset results in a short call instruction (opcode C1h) to the ROM address 008h. This activates the initialization routine $RESET which in turn has to initialize all necessary RAM variables, stack pointers and peripheral configuration registers (see Table 21-1 on page 34). Figure 17-1. Reset Configuration V DD Pull-up CL NRST Reset timer res CL=SYSCL/4 Power-on reset VDD VSS VDD VSS CWD Internal reset Brown-out detection Watchdog res Ext. clock supervisor ExIn 17.1 Power-on Reset and Brown-out Detection The microcontroller block has a fully integrated power-on reset and brown-out detection circuitry. For reset generation no external components are needed. These circuits ensure that the core is held in the reset state until the minimum operating supply voltage has been reached. A reset condition will also be generated should the supply voltage drop momentarily below the minimum operating level except when a power-down mode is activated (the core is in SLEEP mode and the peripheral clock is stopped). In this power-down mode the brown-out detection is disabled. Two values for the brown-out voltage threshold are programmable via the BOT bit in the SC register. 23 4552H-4BMCU-07/07 A power-on reset pulse is generated by a VDD rise across the default BOT voltage level (1.7V). A brown-out reset pulse is generated when VDD falls below the brown-out voltage threshold. Two values for the brown-out voltage threshold are programmable via the BOT bit in the SC register. When the controller runs in the upper supply voltage range with a high system clock frequency, the high threshold must be used. When it runs with a lower system clock frequency, the low threshold and a wider supply voltage range may be chosen. For further details, see the electrical specification and the SC register description for BOT programming. Figure 17-2. Brown-out Detection VDD 2.0V 1.7V td CPU Reset BOT = '1' td CPU Reset BOT = '0' td = 1.5 ms (typically) td t BOT = 1, low brown-out voltage threshold 1.7V (is reset value). BOT = 0, high brown-out voltage threshold 2.0V. 17.1.1 Watchdog Reset The watchdog's function can be enabled at the WDC register and triggers a reset with every watchdog counter overflow. To suppress the watchdog reset, the watchdog counter must be regularly reset by reading the watchdog register address (CWD). The CPU reacts in exactly the same manner as a reset stimulus from any of the above sources. External Clock Supervisor The external input clock supervisor function can be enabled if the external input clock is selected within the CM and SC registers of the clock module. The CPU reacts in exactly the same manner as a reset stimulus from any of the above sources. 17.1.2 18. Voltage Monitor The voltage monitor consists of a comparator with internal voltage reference. It is used to supervise the supply voltage or an external voltage at the VMI pin. The comparator for the supply voltage has three internal programmable thresholds one lower threshold (2.2 V), one middle threshold (2.6 V) and one higher threshold (3.0 V). For external voltages at the VMI pin, the comparator threshold is set to VBG = 1.3 V. The VMS bit indicates if the supervised voltage is below (VMS = 0) or above (VMS = 1) this threshold. An interrupt can be generated when the VMS bit is set or reset to detect a rising or falling slope. A voltage monitor interrupt (INT7) is enabled when the interrupt mask bit (VIM) is reset in the VMC register. 24 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 Figure 18-1. Voltage Monitor V DD Voltage monitor BP41/ VMI IN OUT INT7 VMC : VM2 VM1 VM0 VIM VMST : - - res VMS 18.1 Voltage Monitor Control/ Status Register Primary register address: "F'hex" Bit 3 VMC: Write VMST: Read VM2 - Bit 2 VM1 - Bit 1 VM0 Reserved Bit 0 VIM VMS Reset value: 1111b Reset value: xx11b VM2: VM1: VM0: Table 18-1. VM2 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 Voltage monitor Mode bit 2 Voltage monitor Mode bit 1 Voltage monitor Mode bit 0 Voltage Monitor Modes VM0 1 0 1 0 1 0 1 0 Function Disable voltage monitor External (VIM input), internal reference threshold (1.3V), interrupt with negative slope Not allowed External (VMI input), internal reference threshold (1.3V), interrupt with positive slope Internal (supply voltage), high threshold (3.0V), interrupt with negative slope Internal (supply voltage), middle threshold (2.6V), interrupt with negative slope Internal (supply voltage), low threshold (2.2V), interrupt with negative slope Not allowed VM1 VIM Voltage Interrupt Mask bit VIM = 0, voltage monitor interrupt is enabled VIM = 1, voltage monitor interrupt is disabled Voltage Monitor Status bit VMS = 0, the voltage at the comparator input is below VRef VMS = 1, the voltage at the comparator input is above VRef VMS 25 4552H-4BMCU-07/07 Figure 18-2. Internal Supply Voltage Supervisor VMS = 1 V DD 3.0V 2.6V 2.2V Low threshold Middle threshold High threshold Low threshold Middle threshold High threshold VMS = 0 Figure 18-3. External Input Voltage Supervisor Internal reference level VMI Negative slope VMS = 1 1.3V VMS = 0 Positive slope Interrupt negative slope t VMS = 0 Interrupt positive slope VMS = 1 19. Clock Generation 19.1 Clock Module The microcontroller block contains a clock module with 4 different internal oscillator types: two RC oscillators, one 4-MHz crystal oscillator and one 32-kHz crystal oscillator. The pins OSC1 and OSC2 are the interface to connect a crystal either to the 4-MHz, or to the 32-kHz crystal oscillator. OSC1 can be used as input for external clocks or to connect an external trimming resistor for the RC-oscillator 2. All necessary circuitry, except the crystal and the trimming resistor, is integrated on-chip. One of these oscillator types or an external input clock can be selected to generate the system clock (SYSCL). In applications that do not require exact timing, it is possible to use the fully integrated RC-oscillator 1 without any external components. The RC-oscillator 1 center frequency tolerance is better than 50%. The RC-oscillator 2 is a trimmable oscillator whereby the oscillator frequency can be trimmed with an external resistor attached between OSC1 and VDD. In this configuration, the RC-oscillator 2 frequency can be maintained stable with a tolerance of 15% over the full operating temperature and voltage range. The clock module is programmable via software with the clock management register (CM) and the system configuration register (SC). The required oscillator configuration can be selected with the OS1 bit and the OS0 bit in the SC register. A programmable 4-bit divider stage allows the adjustment of the system clock speed. A special feature of the clock management is that an external oscillator may be used and switched on and off via a port pin for the power-down mode. Before the external clock is switched off, the internal RC-oscillator 1 must be selected with the CCS bit and then the SLEEP mode may be activated. 26 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 In this state an interrupt can wake up the controller with the RC-oscillator, and the external oscillator can be activated and selected by software. A synchronization stage avoids too short clock periods if the clock source or the clock speed is changed. If an external input clock is selected, a supervisor circuit monitors the external input and generates a hardware reset if the external clock source fails or drops below 500 kHz for more than 1 ms. Figure 19-1. Clock Module OSC1 Oscin Ext. clock ExIn RC oscillator 1 ExOut Stop Stop RCOut1 Control IN1 Cin IN2 Divider 4Out Stop /2 /2 /2 /2 SYSCL * RC oscillator2 R Trim RCOut2 Stop 4-MHz oscillator Oscin Oscout OSC2 Oscout 32-kHz oscillator * Oscin Oscout 32Out Osc-Stop CM: Sleep WDL Cin/16 NSTOP CCS CSS1 CSS0 32 kHz SUBCL * mask option SC: BOT --OS1 OS0 Figure 19-2. Clock Modes Clock Source for SYSCL Mode 1 2 3 4 OS1 1 0 1 0 OS0 1 1 0 0 CCS = 1 RC-oscillator 1 (internal) RC-oscillator 1 (internal) RC-oscillator 1 (internal) RC-oscillator 1 (internal) CCS = 0 External input clock RC-oscillator 2 with external trimming resistor 4-MHz oscillator 32-kHz oscillator Clock Source for SUBCL Cin/16 Cin/16 Cin/16 32 kHz The clock module generates two output clocks. One is the system clock (SYSCL) and the other the periphery (SUBCL). The SYSCL can supply the core and the peripherals and the SUBCL can supply only the peripherals with clocks. The modes for clock sources are programmable with the OS1 bit and OS0 bit in the SC register and the CCS bit in the CM register. 19.2 Oscillator Circuits and External Clock Input Stage The microcontroller block series consists of four different internal oscillators: two RC-oscillators, one 4-MHz crystal oscillator, one 32-kHz crystal oscillator and one external clock input stage. 27 4552H-4BMCU-07/07 19.2.1 RC-oscillator 1 Fully Integrated For timing insensitive applications, it is possible to use the fully integrated RC-oscillator 1. It operates without any external components and saves additional costs. The RC-oscillator 1 center frequency tolerance is better than 50% over the full temperature and voltage range. The basic center frequency of the RC-oscillator 1 is fO 3.8 MHz. The RC-oscillator 1 is selected by default after power-on reset. Figure 19-3. RC-oscillator 1 RC oscillator 1 RcOut1 Stop RcOut1 Osc-Stop Control 19.2.2 External Input Clock The OSC1 or OSC2 (mask option) can be driven by an external clock source provided it meets the specified duty cycle, rise and fall times and input levels. Additionally, the external clock stage contains a supervisory circuit for the input clock. The supervisor function is controlled via the OS1, OS0 bit in the SC register and the CCS bit in the CM register. If the external input clock is missing for more than 1 ms and CCS = 0 is set in the CM register, the supervisory circuit generates a hardware reset. Figure 19-4. External Input Clock Ext. input clock Ext. Clock or Ext. OSC2 Clock Clock monitor OSC1 ExIn Stop ExOut RcOut1 Osc-Stop CCS Res Table 19-1. OS1 1 1 x Supervisor Function Control Bits OS0 1 1 0 CCS 0 1 x Supervisor Reset Output (Res) Enable Disable Disable 28 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 19.2.3 RC-oscillator 2 with External Trimming Resistor The RC-oscillator 2 is a high resolution trimmable oscillator whereby the oscillator frequency can be trimmed with an external resistor between OSC1 and VDD. In this configuration, the RC-oscillator 2 frequency can be maintained stable with a tolerance of 10% over the full operating temperature and a voltage range VDD from 2.5V to 6.0V. For example: An output frequency at the RC-oscillator 2 of 2 MHz can be obtained by connecting a resistor Rext = 360 k (see Figure 19-5 on page 29). Figure 19-5. RC-oscillator 2 V DD R ext OSC1 R Trim Stop OSC2 RC oscillator 2 RcOut2 RcOut2 Osc-Stop 19.2.4 4-MHz Oscillator The microcontroller block 4-MHz oscillator options need a crystal or ceramic resonator connected to the OSC1 and OSC2 pins to establish oscillation. All the necessary oscillator circuitry is integrated, except the actual crystal, resonator, C3 and C4. Figure 19-6. 4-MHz Crystal Oscillator OSC1 Oscin * XTAL 4 MHz C1 * C2 mask option 4Out 4-MHz oscillator Oscout OSC2 * Stop 4Out Osc-Stop Figure 19-7. Ceramic Resonator C3 OSC1 Oscin * Cer. Res C1 * C2 mask option 4Out 4-MHz oscillator Oscout C4 * OSC2 Stop 4Out Osc-Stop 29 4552H-4BMCU-07/07 19.2.5 32-kHz Oscillator Some applications require long-term time keeping or low resolution timing. In this case, an on-chip, low power 32-kHz crystal oscillator can be used to generate both the SUBCL and the SYSCL. In this mode, power consumption is greatly reduced. The 32-kHz crystal oscillator can not be stopped while the power-down mode is in operation. Figure 19-8. 32-kHz Crystal Oscillator OSC1 Oscin * XTAL 32 kHz C1 * C2 mask option 32Out 32-kHz oscillator Oscout OSC2 * 32Out Note: Both, the 4-MHz and the 32-kHz crystal oscillator, use an integrated 14 stage divider circuit to stabilize oscillation before the oscillator output is used as system clock. This results in an additional delay of about 4 ms for the 4-MHz crystal and about 500 ms for the 32-kHz crystal. 19.3 Clock Management The clock management register controls the system clock divider and synchronization stage. Writing to this register triggers the synchronization cycle. 19.3.1 Clock Management Register (CM) Auxiliary register address: "3"hex Bit 3 CM: NSTOP Bit 2 CCS Bit 1 CSS1 Bit 0 CSS0 Reset value: 1111b NSTOP Not STOP peripheral clock NSTOP = 0, stops the peripheral clock while the core is in SLEEP mode NSTOP = 1, enables the peripheral clock while the core is in SLEEP mode Core Clock Select CCS = 1, the internal RC-oscillator 1 generates SYSCL CCS = 0, the 4-MHz crystal oscillator, the 32-kHz crystal oscillator, an external clock source or the internal RC-oscillator 2 with the external resistor at OSC1 generates SYSCL dependent on the setting of OS0 and OS1 in the system configuration register Core Speed Select 1 Core Speed Select 0 CCS CSS1 CSS0 30 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 Table 19-2. CSS1 0 1 1 0 Core Speed Select CSS0 0 1 0 1 Divider 16 8 4 2 Note - Reset value - - 19.3.2 System Configuration Register (SC) Primary register address: "3"hex Bit 3 SC: write BOT Bit 2 - Bit 1 OS1 Bit 0 OS0 Reset value: 1x11b BOT OS1 OS0 Brown-Out Threshold BOT = 1, low brown-out voltage threshold (1.7V) BOT = 0, high brown-out voltage threshold (2.0V) Oscillator Select 1 Oscillator Select 0 Table 19-3. Mode 1 2 3 4 Note: 1 0 1 0 Oscillator Select OS0 1 1 0 0 Input for SUBCL Cin/16 Cin/16 Cin/16 32 kHz Selected Oscillators RC-oscillator 1 and external input clock RC-oscillator 1 and RC-oscillator 2 RC-oscillator 1 and 4-MHz crystal oscillator RC-oscillator 1 and 32-kHz crystal oscillator OS1 If bit CCS = 0 in the CM register, the RC-oscillator 1 always stops. 20. Power-down Modes The sleep mode is a shut-down condition which is used to reduce the average system power consumption in applications where the microcontroller is not fully utilized. In this mode, the system clock is stopped. The sleep mode is entered via the SLEEP instruction. This instruction sets the interrupt enable bit (I) in the condition code register to enable all interrupts and stops the core. During the sleep mode the peripheral modules remain active and are able to generate interrupts. The microcontroller exits the sleep mode by carrying out any interrupt or a reset. The sleep mode can only be kept when none of the interrupt pending or active register bits are set. The application of the $AUTOSLEEP routine ensures the correct function of the sleep mode. For standard applications use the $AUTOSLEEP routine to enter the power-down mode. Using the SLEEP instruction instead of the $AUTOSLEEP following an I/O instruction requires to insert 3 non-I/O instruction cycles (for example NOP NOP NOP) between the IN or OUT command and the SLEEP command. 31 4552H-4BMCU-07/07 The total power consumption is directly proportional to the active time of the microcontroller. For a rough estimation of the expected average system current consumption, the following formula should be used: Itotal (VDD, fsyscl) = ISleep + (IDD x tactive/ttotal) IDD depends on VDD and fsyscl The microcontroller block has various power-down modes. During the sleep mode the clock for the MARC4 core is stopped. With the NSTOP-bit in the clock management register (CM), it is programmable if the clock for the on-chip peripherals is active or stopped during the sleep mode. If the clock for the core and the peripherals is stopped, the selected oscillator is switched off. An exception is the 32-kHz oscillator, if it is selected it runs continuously independent of the NSTOP-bit. If the oscillator is stopped or the 32-kHz oscillator is selected, power consumption is extremely low. Table 20-1. Power-down Modes CPU Core RUN SLEEP SLEEP Osc-Sto p(1) NO NO YES Brown-out Function Active Active STOP RC-oscillator 1 RC-oscillator 2 4-MHz Oscillator RUN RUN STOP 32-kHz Oscillator RUN RUN RUN External Input Clock YES YES STOP Mode Active Power-down SLEEP Note: 1. Osc-Stop = SLEEP and NSTOP and WDL 21. Peripheral Modules 21.1 Addressing Peripherals Accessing the peripheral modules takes place via the I/O bus (see Figure 21-1 on page 33). The IN or OUT instructions allow direct addressing of up to 16 I/O modules. A dual register addressing scheme has been adopted to enable direct addressing of the primary register. To address the auxiliary register, the access must be switched with an auxiliary switching module. Thus, a single IN (or OUT) to the module address will read (or write into) the module primary register. Accessing the auxiliary register is performed with the same instruction preceded by writing the module address into the auxiliary switching module. Byte wide registers are accessed by multiple IN- (or OUT-) instructions. For more complex peripheral modules, with a larger number of registers, extended addressing is used. In this case, a bank of up to 16 subport registers are indirectly addressed with the subport address. The first OUT instruction writes the subport address to the subaddress register, the second IN or OUT instruction reads data from or writes data to the addressed subport. 32 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 Figure 21-1. Example of I/O Addressing Module ASW Module M1 (Address Pointer) Subaddress Reg. Auxiliary Switch Module Bank of Primary Reg. Subport Fh 1 Module M2 Aux. Reg. 5 Module M3 Subport Eh Subport 1 Subport 0 2 Primary Reg. Primary Reg. 3 4 Primary Reg. 6 I/O bus to other modules Indirect Subport Access (Subport Register Write) 1 Addr. (SPort) Addr. (M1) OUT 2 SPort _Data Addr. (M1) OUT 3 Dual Register Access (Primary Register Write) Prim._Data Addr. (M2) (Auxiliary Register Write) 4 Addr. (M2) Addr. (ASW) OUT 5 Aux._Data Addr. (M2) OUT 6 OUT Single Register Access (Primary Register Write) 6 Prim._Data Addr.(M3) OUT (Primary Register Read) Addr. (M3) IN (Subport Register Read) 1 Addr. (SPort) Addr. (M1) OUT 2 Addr. (M1) IN Example of qFORTH program code (Primary Register Read) 3 Addr. (M2) (Auxiliary Register Read) 4 Addr. (M2) Addr. (ASW) OUT 5 Addr. (M2) IN IN (Subport Register Write Byte) 1 Addr. (SPort) Addr. (M1) OUT 2 SPort _Data(lo) Addr. (M1) OUT 2 SPort _Data(hi) Addr. (M1) OUT (Subport Register Read Byte) 1 Addr. (SPort) Addr. (M1) OUT 2 2 Addr. (M1) IN (hi) Addr. (M1) IN (lo) (Auxiliary Register Write Byte) 4 5 5 Addr. (M2) Addr. (ASW) OUT OUT OUT Aux._Data (lo) Addr. (M2) Aux._Data (hi) Addr. (M2) Addr.(ASW) = Auxiliary Switch Module address Addr.(Mx) = Module Mx address Addr.(SPort) = Subport address Prim._Data = Data to be written into Primary Register Aux._Data = Data to be written into Auxiliary Register Prim._Data(lo)= Data to be written into Auxiliary Register (low nibble) Prim._Data(hi) = Data to be written into Auxiliary Register (high nibble) SPort_Data(lo) = Data to be written into SubPort (low nibble) SPort_Data(hi) = Data to be written into SubPort (high nibble) (lo) = SPort_Data (low nibble) (hi) = SPort_Data (high nibble) 33 4552H-4BMCU-07/07 Table 21-1. Peripheral Addresses Name P1DAT P2DAT Auxiliary P2CR SC CWD Auxiliary CM P4DAT Auxiliary P4CR P5DAT Auxiliary P5CR P6DAT Auxiliary P6CR T12SUB Subport address 0 1 2 3 4 5 6 7 8 9 A B-F T2C T2M1 T2M2 T2CM T2CO1 T2CO2 - - T1C1 T1C2 WDC - ASW STB SRB Auxiliary SIC1 SISC Auxiliary SIC2 T3SUB Subport address 0 1 2 3 4 4 5 6-F T3M T3CS T3CM1 T3CM2 T3CO1 T3CP T3CO2 - - - - - - - W W W W W R W - W R - - W R 1111b 1111b 0000b 0000b 1111 1111b xxxx xxxxb 1111 1111b - 0000b x000b - - 1111b xx11b Timer 3 mode register Timer 3 clock select register Timer 3 compare mode register 1 Timer 3 compare mode register 2 Timer 3 compare register 1 (byte) Timer 3 capture register (byte) Timer 3 compare register 2 (byte) Reserved Timer 3 control register Timer 3 status register Reserved Reserved Voltage monitor control register Voltage monitor status register M1 M1 M1 M1 M1 M1 M1 - M3 M3 - - M3 M3 W W W W W W - - W W W - W W R W W/R W W/R 0000b 1111b 1111b 0000b 1111b 1111 1111b - - 1111b x111b 1111b - 1111b xxxx xxxxb xxxx xxxxb 1111b 1x11b 1111b - Timer 2 control register Timer 2 mode register 1 Timer 2 mode register 2 Timer 2 compare mode register Timer 2 compare register 1 Timer 2 compare register 2 (byte) Reserved Reserved Timer 1 control register 1 Timer 1 control register 2 Watchdog control register Reserved Auxiliary/switch register Serial transmit buffer (byte) Serial receive buffer (byte) Serial interface control register 1 Serial interface status/control register Serial interface control register 2 Data to/from Timer 3 subport M1 M1 M1 M1 M1 M1 - - M1 M1 M1 - ASW M2 M2 M2 M2 M2 M1 Write/ Read W/R W/R W W R W W/R W W/R W W/R W W Reset Value 1xx1b 1111b 1111b 1x11b xxxxb 1111b 1111b 1111 1111b 1111b 1111 1111b 1xx1b 1111b - Register Function Port 1 - data register/input data Port 2 - data register/pin data Port 2 - control register System configuration register Watchdog reset Clock management register Port 4 - data register/pin data Port 4 - control register (byte) Port 5 - data register/pin data Port 5 - control register (byte) Port 6 - data register/pin data Port 6 - control register (byte) Data to Timer 1/2 subport Module Type M3 M2 M2 M3 M3 M2 M2 M2 M2 M2 M2 M2 M1 Port Address 1 2 3 4 5 6 7 8 9 A B C D E F T3C T3ST - - VMC VMST 34 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 22. Bi-directional Ports With the exception of Port 1 and Port 6, all other ports (2, 4 and 5) are 4 bits wide. Port 1 and Port 6 have a data width of 2 bits (bit 0 and bit 3). All ports may be used for data input or output. All ports are equipped with Schmitt trigger inputs and a variety of mask options for open-drain, open-source, full-complementary outputs, pull-up and pull-down transistors. All Port Data Registers (PxDAT) are I/O mapped to the primary address register of the respective port address and the Port Control Register (PxCR), to the corresponding auxiliary register. There are five different directional ports available: Port 1 Port 2 Port 5 Port 4 Port 6 2-bit wide bi-directional port with automatic full bus width direction switching. 4-bit wide bitwise-programmable I/O port. 4-bit wide bitwise-programmable bi-directional port with optional strong pull-ups and programmable interrupt logic. 4-bit wide bitwise-programmable bi-directional port also provides the I/O interface to Timer 2, SSI, voltage monitor input and external interrupt input. 2-bit wide bitwise-programmable bi-directional port also provides the I/O interface to Timer 3 and external interrupt input. 22.1 Bi-directional Port 1 In Port 1 the data direction register is not independently software programmable, the direction of the complete port being switched automatically when an I/O instruction occurs (see Figure 22-1 on page 36). The port is switched to output mode via an OUT instruction and to input via an IN instruction. The data written to a port will be stored into the output data latches and appears immediately at the port pin following the OUT instruction. After RESET all output latches are set to "1" and the port is switched to input mode. An IN instruction reads the condition of the associated pins. Note: Care must be taken when switching the bi-directional port from output to input. The capacitive pin loading at this port in conjunction with the high resistance pull-ups may cause the CPU to read the contents of the output data register rather than the external input state. To avoid this, one of the following programming techniques should be used: Use two IN-instructions and DROP the first data nibble. The first IN switches the port from output to input and the DROP removes the first invalid nibble. The second IN reads the valid pin state. Use an OUT instruction followed by an IN instruction. Via the OUT instruction, the capacitive load is charged or discharged depending on the optional pull-up/pull-down configuration. Write a "1" for pins with pull-up resistors and a "0" for pins with pull-down resistors. 35 4552H-4BMCU-07/07 Figure 22-1. Bi-directional Port 1 V DD I/O Bus * (Data out) D Q Static pull-up * Switched pull-up P1DATy R Reset (Direction) OUT S IN R Master reset NQ Q BP1y * V DD * Static pull-down *) Mask options Switched pull-down 22.2 Bi-directional Port 2 As all other bi-directional ports, this port includes a bitwise programmable Control Register (P2CR), which enables the individual programming of each port bit as input or output. It also opens up the possibility of reading the pin condition when in output mode. This is a useful feature for self testing and for serial bus applications. Port 2, however, has an increased drive capability and an additional low resistance pull-up/-down transistor mask option. Care should be taken connecting external components to BP20/NTE. During any reset phase, the BP20/NTE input is driven towards VDD by an additional internal strong pull-up transistor. This pin must not be pulled down (active or passive) to VSS during reset by any external circuitry representing a resistor of less than 150 k. This prevents the circuit from unintended switching to test mode enable through the application circuitry at pin BP20/NTE. Resistors less than 150 k might lead to an undefined state of the internal test logic thus disabling the application firmware. To avoid any conflict with the optional internal pull-down transistors, BP20 handles the pull-down options in a different way than all other ports. BP20 is the only port that switches off the pull-down transistors during reset. 36 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 Figure 22-2. Bi-directional Port 2 I/O Bus V DD Switched pull-up Static Pull-up * (Data out) I/O Bus D S Master reset I/O Bus Q P2DATy * * BP2y * V DD D SQ P2CRy * * Static Pull-down (Direction) * Mask options Switched pull-down 22.2.1 Port 2 Data Register (P2DAT) Primary register address: "2"hex Bit 3 * P2DAT3 Bit 2 P2DAT2 Bit 1 P2DAT1 Bit 0 P2DAT0 Reset value: 1111b * Bit 3 -> MSB, Bit 0 -> LSB 22.2.2 Port 2 Control Register (P2CR) Auxiliary register address: "2"hex Bit 3 P2CR3 Bit 2 P2CR2 Bit 1 P2CR1 Bit 0 P2CR0 Reset value: 1111b Value: 1111b means all pins in input mode Table 22-1. Code 3210 xxx1 xxx0 xx1x xx0x x1xx x0xx 1xxx 0xxx Port 2 Control Register Function BP20 in input mode BP20 in output mode BP21 in input mode BP21 in output mode BP22 in input mode BP22 in output mode BP23 in input mode BP23 in output mode 37 4552H-4BMCU-07/07 22.3 Bi-directional Port 5 As all other bi-directional ports, this port includes a bitwise programmable Control Register (P5CR), which allows the individual programming of each port bit as input or output. It also opens up the possibility of reading the pin condition when in output mode. This is a useful feature for self testing and for serial bus applications. The port pins can also be used as external interrupt inputs (see Figure 22-3 and Figure 22-4). The interrupts (INT1 and INT6) can be masked or independently configured to trigger on either edge. The interrupt configuration and port direction is controlled by the Port 5 Control Register (P5CR). An additional low resistance pull-up/-down transistor mask option provides an internal bus pull-up for serial bus applications. The Port 5 Data Register (P5DAT) is I/O mapped to the primary address register of address "5"h and the Port 5 Control Register (P5CR) to the corresponding auxiliary register. The P5CR is a byte-wide register and is configured by writing first the low nibble and then the high nibble (see section "Addressing Peripherals" on page 32). Figure 22-3. Bi-directional Port 5 I/O Bus Switched pull-up V DD * V DD (Data out) I/O Bus D Q P5DATy S Master reset IN enable * pull-up Static * BP5y * V DD * * Static Pull-down * Mask options Switched pull-down Figure 22-4. Port 5 External Interrupts INT1 Data in BP52 INT6 Data in BP51 Bidir. Port IN_Enable Bidir. Port IN_Enable I/O-bus I/O-bus Data in BP53 Data in BP50 Bidir. Port IN_Enable Decoder Decoder Decoder Decoder Bidir. Port IN_Enable P5CR: P53M2 P53M1 P52M2 P52M1 P51M2 P51M1 P50M2 P50M1 38 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 22.3.1 Port 5 Data Register (P5DAT) Primary register address: "5"hex Bit 3 P5DAT3 Bit 2 P5DAT2 Bit 1 P5DAT1 Bit 0 P5DAT0 Reset value: 1111b 22.3.2 Port 5 Control Register (P5CR) Byte Write Auxiliary register address: "5"hex Bit 3 First write cycle Second write cycle P51M2 Bit 7 P53M2 Bit 2 P51M1 Bit 6 P53M1 Bit 1 P50M2 Bit 5 P52M2 Bit 0 P50M1 Bit 4 P52M1 Reset value: 1111b Reset value: 1111b P5xM2, P5xM1 - Port 5x interrupt mode/direction code Table 22-2. Code 3210 xx11 xx01 xx10 xx00 11xx 01xx 10xx 00xx Port 5 Control Register First Write Cycle Code 3210 xx11 xx01 xx10 xx00 11xx 01xx 10xx 00xx Second Write Cycle Function BP52 in input mode - interrupt disabled BP52 in input mode - rising edge interrupt BP52 in input mode - falling edge interrupt BP52 in output mode - interrupt disabled BP53 in input mode - interrupt disabled BP53 in input mode - rising edge interrupt BP53 in input mode - falling edge interrupt BP53 in output mode - interrupt disabled Auxiliary Address: "5"hex Function BP50 in input mode - interrupt disabled BP50 in input mode - rising edge interrupt BP50 in input mode - falling edge interrupt BP50 in output mode - interrupt disabled BP51 in input mode - interrupt disabled BP51 in input mode - rising edge interrupt BP51 in input mode - falling edge interrupt BP51 in output mode - interrupt disabled 39 4552H-4BMCU-07/07 22.4 Bi-directional Port 4 The bi-directional Port 4 is a bitwise configurable I/O port and provides the external pins for the Timer 2, SSI and the voltage monitor input (VMI). As a normal port, it performs in exactly the same way as bi-directional Port 2 (see Figure 22-5). Two additional multiplexes allow data and port direction control to be passed over to other internal modules (Timer 2, VM or SSI). The I/O-pins for SC and SD line have an additional mode to generate an SSI-interrupt. All four Port 4 pins can be individually switched by the P4CR-register. Figure 22-5 shows the internal interfaces to bi-directional Port 4. Figure 22-5. Bi-directional Port 4 and Port 6 I/O Bus Intx PxMRy V DD * V DD Switched pull-up * pull-up Static PIn POut I/O Bus D Q PxDATy S Master reset I/O Bus D * BPxy * (Direction) V DD S Q Switched pull-down * * Static pull-down PxCRy PDir * Mask options 22.4.1 Port 4 Data Register (P4DAT) Primary register address: "4"hex Bit 3 P4DAT3 Bit 2 P4DAT2 Bit 1 P4DAT1 Bit 0 P4DAT0 Reset value: 1111b 22.4.2 Port 4 Control Register (P4CR) Byte Write Auxiliary register address: "4"hex Bit 3 First write cycle Second write cycle P41M2 Bit 7 P43M2 Bit 2 P41M1 Bit 6 P43M1 Bit 1 P40M2 Bit 5 P42M2 Bit 0 P40M1 Bit 4 P42M1 Reset value: 1111b Reset value: 1111b P4xM2, P4xM1 - Port 4x interrupt mode/direction code 40 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 Table 22-3. Port 4 Control Register Second Write Cycle Code 3210 xx11 xx10 xx0x 11xx 10xx 01xx 00xx - Function BP42 in input mode BP42 in output mode BP42 enable alternate function (T2O for Timer 2) BP43 in input mode BP43 in output mode BP43 enable alternate function (SD for SSI) BP43 enable alternate function (falling edge interrupt input for INT3) - Auxiliary Address: "4"hex First Write Cycle Code 3210 xx11 xx10 xx01 xx00 11xx 10xx 01xx 00xx Function BP40 in input mode BP40 in output mode BP40 enable alternate function (SC for SSI) BP40 enable alternate function (falling edge interrupt input for INT3) BP41 in input mode BP41 in output mode BP41 enable alternate function (VMI for voltage monitor input) BP41 enable alternate function (T2I external clock input for Timer 2) 22.5 Bi-directional Port 6 The bi-directional Port 6 is a bitwise configurable I/O port and provides the external pins for the Timer 3. As a normal port, it performs in exactly the same way as bi-directional Port 6 (see Figure 22-5 on page 40). Two additional multiplexes allow data and port direction control to be passed over to other internal module (Timer 3). The I/O pin for T3I line has an additional mode to generate a Timer 3 interrupt. All two Port 6 pins can be individually switched by the P6CR register. Figure 22-5 on page 40 shows the internal interfaces to bi-directional Port 6. 22.5.1 Port 6 Data Register (P6DAT) Primary register address: "6"hex Bit 3 P6DAT3 Bit 2 - Bit 1 - Bit 0 P6DAT0 Reset value: 1xx1b 22.5.2 Port 6 Control Register (P6CR) Auxiliary register address: "6"hex Bit 3 P63M2 Bit 2 P63M1 Bit 1 P60M2 Bit 0 P60M0 Reset value: 1111b P6xM2, P6xM1 - Port 6x interrupt mode/direction code 41 4552H-4BMCU-07/07 Table 22-4. Code 3210 xx11 xx10 xx0x Port 6 Control Register Auxiliary Address: "6"hex Function BP60 in input mode BP60 in output mode BP60 enable alternate port function (T3O for Timer 3) Code 3210 11xx 10xx 0xxx Write Cycle Function BP63 in input mode BP63 in output mode BP63 enable alternate port function (T3I for Timer 3) 22.6 Universal Timer/Counter/ Communication Module (UTCM) The Universal Timer/counter/Communication Module (UTCM) consists of three timers (Timer 1,Timer 2, Timer 3) and a Synchronous Serial Interface (SSI). * Timer 1 is an interval timer that can be used to generate periodical interrupts and as prescaler for Timer 2, Timer 3, the serial interface and the watchdog function. * Timer 2 is an 8/12-bit timer with an external clock input (T2I) and an output (T2O). * Timer 3 is an 8-bit timer/counter with its own input (T3I) and output (T3O). * The SSI operates as two wire serial interface or as shift register for modulation and demodulation. The modulator and demodulator units work together with the timers and shift the data bits into or out of the shift register. There is a multitude of modes in which the timers and the serial interface can work together. 42 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 Figure 22-6. UTCM Block Diagram SYSCL SUBCL from clock module Timer 1 Watchdog MUX Interval / Prescaler NRST INT2 T1OUT Timer 3 Capture 3 Control Demodulator 3 Modulator 3 INT5 T3O T3I MUX 8-bit Counter 3 Compare 3/1 Compare 3/2 TOG3 Timer 2 4-bit Counter 2/1 MUX Compare 2/1 Modulator 2 I/O bus T2O POUT T2I MUX DCG Control 8-bit Counter 2/2 INT4 Compare 2/2 TOG2 SSI Receive buffer SCL MUX 8-bit shift register Transmit buffer Control INT3 SC SD 22.7 Timer 1 The Timer 1 is an interval timer which can be used to generate periodical interrupts and as prescaler for Timer 2, Timer 3, the serial interface and the watchdog function. The Timer 1 consists of a programmable 14-stage divider that is driven by either SUBCL or SYSCL. The timer output signal can be used as prescaler clock or as SUBCL and as source for the Timer 1 interrupt. Because of other system requirements, the Timer 1 output T1OUT is synchronized with SYSCL. Therefore, in the power-down mode SLEEP (CPU core -> sleep and OSC-Stop -> yes), the output T1OUT is stopped (T1OUT = 0). Nevertheless, the Timer 1 can be active in SLEEP and generate Timer 1 interrupts. The interrupt is maskable via the T1IM bit and the SUBCL can be bypassed via the T1BP bit of the T1C2 register. The time interval for the timer output can be programmed via the Timer 1 control register T1C1. 43 4552H-4BMCU-07/07 This timer starts running automatically after any power-on reset! If the watchdog function is not activated, the timer can be restarted by writing into the T1C1 register with T1RM = 1. Timer 1 can also be used as a watchdog timer to prevent a system from stalling. The watchdog timer is a 3-bit counter that is supplied by a separate output of Timer 1. It generates a system reset when the 3-bit counter overflows. To avoid this, the 3-bit counter must be reset before it overflows. The application software has to accomplish this by reading the CWD register. After power-on reset the watchdog must be activated by software in the $RESET initialization routine. There are two watchdog modes, in one mode the watchdog can be switched on and off by software, in the other mode the watchdog is active and locked. This mode can only be stopped by carrying out a system reset. The watchdog timer operation mode and the time interval for the watchdog reset can be programmed via the watchdog control register (WDC). Figure 22-7. Timer 1 Module SYSCL SUBCL WDCL CL1 MUX Prescaler 14 bit Watchdog 4 bit NRST INT2 T1CS T1MUX T1BP T1IM T1OUT Figure 22-8. Timer 1 and Watchdog T1C1 T1RM T1C2 T1C1 T1C0 3 Write of the T1C1 register T1IM=0 T1MUX T1C2 T1BP T1IM Decoder MUX for interval timer T1IM=1 INT2 T1OUT RES Q1 Q2 Q3 Q4 Q5 CL1 CL Q6 Q8 Q8 Q11 Q11 Q14 SUBCL Q14 Watchdog Divider / 8 Decoder 2 WDC WDL WDR WDT1 WDT0 MUX for watchdog timer WDCL RES Read of the CWD register Divider RESET RESET (NRST) Watchdog mode control 44 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 22.7.1 Timer 1 Control Register 1 (T1C1) Address: "7"hex - Subaddress: "8"hex Bit 3 * T1RM Bit 2 T1C2 Bit 1 T1C1 Bit 0 T1C0 Reset value: 1111b * Bit 3 -> MSB, Bit 0 -> LSB T1RM T1C2 T1C1 T1C0 Timer 1 Restart Mode T1RM = 0, write access without Timer 1 restart .......T1RM = 1, write access with Timer 1 restart Note: If WDL = 0, Timer 1 restart is impossible Timer 1 Control bit 2 Timer 1 Control bit 1 Timer 1 Control bit 0 The three bits T1C[2:0] select the divider for Timer 1. The resulting time interval depends on this divider and the Timer 1 input clock source. The timer input can be supplied by the system clock, the 32-kHz oscillator or via the clock management. If the clock management generates the SUBCL, the selected input clock from the RC oscillator, 4-MHz oscillator or an external clock is divided by 16. Table 22-5. T1C2 0 0 0 0 1 1 1 1 T1C1 0 0 1 1 0 0 1 1 Timer 1 Control Bits T1C0 0 1 0 1 0 1 0 1 Divider 2 4 8 16 32 256 2048 16384 Time Interval with SUBCL SUBCL/2 SUBCL/4 SUBCL/8 SUBCL/16 SUBCL/32 SUBCL/256 SUBCL/2048 SUBCL/16384 Time Interval with SUBCL = 32 kHz 61 s 122 s 244 s 488 s 0.977 ms 7.812 ms 62.5 ms 500 ms Time Interval with SYSCL = 2/1 MHz 1 s/2 s 2 s/4 s 4 s/8 s 8 s/16 s 16 s/32 s 128 s/256 s 1024 s/2048 s 8192 s/16384 s 45 4552H-4BMCU-07/07 22.7.2 Timer 1 Control Register 2 (T1C2) Address: "7"hex - Subaddress: "9"hex Bit 3 * - Bit 2 T1BP Bit 1 T1CS Bit 0 T1IM Reset value: x111b * Bit 3 -> MSB, Bit 0 -> LSB T1BP Timer 1 SUBCL ByPassed T1BP = 1, TIOUT = T1MUX T1BP = 0, T1OUT = SUBCL Timer 1 input Clock Select T1CS = 1, CL1 = SUBCL (see Figure 22-7 on page 44) T1CS = 0, CL1 = SYSCL (see Figure 22-7 on page 44) Timer 1 Interrupt Mask T1IM = 1, disables Timer 1 interrupt T1IM = 0, enables Timer 1 interrupt T1CS T1IM 22.7.3 Watchdog Control Register (WDC) Address: "7"hex - Subaddress: "A"hex Bit 3 * WDL Bit 2 WDR Bit 1 WDT1 Bit 0 WDT0 Reset value: 1111b * Bit 3 -> MSB, Bit 0 -> LSB WDL WatchDog Lock mode WDL = 1, the watchdog can be enabled and disabled by using the WDR-bit WDL = 0, the watchdog is enabled and locked. In this mode the WDR-bit has no effect. After the WDL-bit is cleared, the watchdog is active until a system reset or power-on reset occurs. WatchDog Run and stop mode WDR = 1, the watchdog is stopped/disabled WDR = 0, the watchdog is active/enabled WatchDog Time 1 WatchDog Time 0 WDR WDT1 WDT0 Both these bits control the time interval for the watchdog reset. Table 22-6. WDT1 0 0 1 1 Watchdog Time Control Bits WDT0 0 1 0 1 Divider 512 2048 16384 131072 Delay Time to Reset with SUBCL = 32 kHz 15.625 ms 62.5 ms 0.5 s 4s Delay Time to Reset with SYSCL = 2/1 MHz 0.256 ms/0.512 ms 1.024 ms/2.048 ms 8.2 ms/16.4 ms 65.5 ms/131 ms 46 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 22.8 Timer 2 8-/12-bit Timer for: * Interrupt, square-wave, pulse and duty cycle generation * Baud-rate generation for the internal shift register * Manchester and Biphase modulation together with the SSI * Carrier frequency generation and modulation together with the SSI Timer 2 can be used as an interval timer for interrupt generation, as signal generator or as baud-rate generator and modulator for the serial interface. It consists of a 4-bit and an 8-bit up counter stage which both have compare registers. The 4-bit counter stages of Timer 2 are cascadable as a 12-bit timer or as an 8-bit timer with 4-bit prescaler. The timer can also be configured as an 8-bit timer and a separate 4-bit prescaler. The Timer 2 input can be supplied via the system clock, the external input clock (T2I), the Timer 1 output clock, the Timer 3 output clock or the shift clock of the serial interface. The external input clock T2I is not synchronized with SYSCL. Therefore, it is possible to use Timer 2 with a higher clock speed than SYSCL. Furthermore, with that input clock the Timer 2 operates in the power-down mode SLEEP (CPU core -> sleep and OSC-Stop -> yes) as well as in the POWER-DOWN (CPU core -> sleep and OSC-Stop -> no). All other clock sources supply no clock signal in SLEEP if NSTOP = 0. The 4-bit counter stages of Timer 2 have an additional clock output (POUT). Its output has a modulator stage that allows the generation of pulses as well as the generation and modulation of carrier frequencies. The Timer 2 output can modulate with the shift register data output to generate Biphase- or Manchester code. If the serial interface is used to modulate a bitstream, the 4-bit stage of Timer 2 has a special task. The shift register can only handle bitstream lengths divisible by 8. For other lengths, the 4-bit counter stage can be used to stop the modulator after the right bitcount is shifted out. If the timer is used for carrier frequency modulation, the 4-bit stage works together with an additional 2-bit duty cycle generator like a 6-bit prescaler to generate carrier frequency and duty cycle. The 8-bit counter is used to enable and disable the modulator output for a programmable count of pulses. For programming the time interval, the timer has a 4-bit and an 8-bit compare register. For programming the timer function, it has four mode and control registers. The comparator output of stage 2 is controlled by a special compare mode register (T2CM). This register contains mask bits for the actions (counter reset, output toggle, timer interrupt) which can be triggered by a compare match event or the counter overflow. This architecture enables the timer function for various modes. The Timer 2 has a 4-bit compare register (T2CO1) and an 8-bit compare register (T2CO2). Both these compare registers are cascadable as a 12-bit compare register, or 8-bit compare register and 4-bit compare register. For 12-bit compare data value: For 8-bit compare data value: For 4-bit compare data value: m = x +1 n = y +1 l = z +1 0 x 4095 0 y 255 0 z 15 47 4552H-4BMCU-07/07 Figure 22-9. Timer 2 I/O-bus P4CR T2I T2M1 T2M2 DCGO SYSCL T1OUT TOG3 SCL CL2/1 4-bit Counter 2/1 RES OVF1 POUT CL2/2 T2O DCG 8-bit Counter 2/2 RES OVF2 TOG2 OUTPUT M2 MOUT T2C Compare 2/1 CM1 Control Compare 2/2 INT4 to Modulator 3 T2CO1 SSI POUT T2CM T2CO2 Biphase-, Manchestermodulator Timer 2 modulator output-stage SO I/O-bus SSI Control SSI 22.9 22.9.1 Timer 2 Modes Mode 1: 12-bit Compare Counter The 4-bit stage and the 8-bit stage work together as a 12-bit compare counter. A compare match signal of the 4-bit and the 8-bit stage generates the signal for the counter reset, toggle flip-flop or interrupt. The compare action is programmable via the compare mode register (T2CM). The 4-bit counter overflow (OVF1) supplies the clock output (POUT) with clocks. The duty cycle generator (DCG) has to be bypassed in this mode. Figure 22-10. 12-bit Compare Counter POUT (CL2/1 /16) CL2/1 OVF2 TOG2 RES INT4 4-bit counter RES DCG 8-bit counter 4-bit compare CM1 8-bit compare CM2 Timer 2 output mode and T2OTM-bit 4-bit register T2D1, 0 8-bit register T2RM T2OTM T2IM T2CTM 48 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 22.9.2 Mode 2: 8-bit Compare Counter with 4-bit Programmable Prescaler Figure 22-11. 8-bit Compare Counter DCGO POUT CL2/1 OVF2 4-bit counter RES DCG 8-bit counter RES TOG2 INT4 4-bit compare CM1 8-bit compare CM2 Timer 2 output mode and T2OTM-bit 4-bit register T2D1, 0 8-bit register T2RM T2OTM T2IM T2CTM The 4-bit stage is used as programmable prescaler for the 8-bit counter stage. In this mode, a duty cycle stage is also available. This stage can be used as an additional 2-bit prescaler or for generating duty cycles of 25%, 33% and 50%. The 4-bit compare output (CM1) supplies the clock output (POUT) with clocks. 22.9.3 Mode 3/4: 8-bit Compare Counter and 4-bit Programmable Prescaler Figure 22-12. 4-/8-bit Compare Counter DCGO T2I SYSCL CL2/2 DCG 8-bit counter OVF2 TOG2 RES INT4 CM2 Timer 2 output mode and T2OTM-bit P4CR P41M2, 1 T2D1, 0 8-bit compare 8-bit register T2RM T2OTM T2IM T2CTM TOG3 T1OUT SYSCL SCL MUX CL2/1 4-bit counter RES CM1 POUT 4-bit compare T2CS1, 0 4-bit register In these modes the 4-bit and the 8-bit counter stages work independently as a 4-bit prescaler and an 8-bit timer with an 2-bit prescaler or as a duty cycle generator. Only in the mode 3 and mode 4, can the 8-bit counter be supplied via the external clock input (T2I) which is selected via the P4CR register. The 4-bit prescaler is started via activating of mode 3 and stopped and reset in mode 4. Changing mode 3 and 4 has no effect for the 8-bit timer stage. The 4-bit stage can be used as prescaler for Timer 3, the SSI or to generate the stop signal for modulator 2 and modulator 3. 49 4552H-4BMCU-07/07 22.10 Timer 2 Output Modes The signal at the timer output is generated via modulator 2. In the toggle mode, the compare match event toggles the output T2O. For high resolution duty cycle modulation 8 bits or 12 bits can be used to toggle the output. In the duty cycle burst modulator modes the DCG output is connected to T2O and switched on and off either by the toggle flip-flop output or the serial data line of the SSI. Modulator 2 also has two modes to output the content of the serial interface as Biphase or Manchester code. The modulator output stage can be configured by the output control bits in the T2M2 register. The modulator is started with the start of the shift register (SIR = 0) and stopped either by carrying out a shift register stop (SIR = 1) or compare match event of stage 1 (CM1) of Timer 2. For this task, Timer 2 mode 3 must be used and the prescaler has to be supplied with the internal shift clock (SCL). Figure 22-13. Timer 2 Modulator Output Stage DCGO SO TOG2 RE Biphase/ Manchester modulator Toggle S1 RES/SET Modulator3 OMSK T2M2 T2OS2, 1, 0 T2TOP M2 M2 S3 S2 T2O SSI CONTROL FE 22.11 Timer 2 Output Signals 22.11.1 Timer 2 Output Mode 1 Toggle Mode A: A Timer 2 compare match toggles the output flip-flop (M2) -> T2O Figure 22-14. Interrupt Timer/Square Wave Generator - the Output Toggles with Each Edge Compare Match Event Input Counter 2 T2R 0 0 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 Counter 2 CMx INT4 T2O 50 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 Toggle Mode B: A Timer 2 compare match toggles the output flip-flop (M2) -> T2O Figure 22-15. Pulse Generator - the Timer Output Toggles with the Timer Start if the T2TS bit Is Set Input Counter 2 T2R 0 0 0 1 2 3 4 5 6 7 4095/ 255 0 1 2 3 4 5 6 Counter 2 CMx INT4 T2O Toggle by start T2O Toggle Mode C: A Timer 2 compare match toggles the output flip-flop (M2) -> T2O Figure 22-16. Pulse Generator - the Timer Toggles with Timer Overflow and Compare Match Input Counter 2 T2R 0 0 0 1 2 3 4 5 6 7 4095/ 255 0 1 2 3 4 5 6 Counter 2 CMx OVF2 INT4 T2O 51 4552H-4BMCU-07/07 22.11.2 Timer 2 Output Mode 2 Duty Cycle Burst Generator 1: The DCG output signal (DCGO) is given to the output, and gated by the output flip-flop (M2) Figure 22-17. Carrier Frequency Burst Modulation with Timer 2 Toggle Flip-flop Output DCGO 1 2 0 1 2 0 1 2 3 4 5 0 1 2 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 Counter 2 TOG2 M2 T2O Counter = compare register (=2) 22.11.3 Timer 2 Output Mode 3 Duty Cycle Burst Generator 2: The DCG output signal (DCGO) is given to the output, and gated by the SSI internal data output (SO) Figure 22-18. Carrier Frequency Burst Modulation with the SSI Data Output DCGO 1201201201201201201201201201201201201201 Counter 2 Counter = compare register (=2) TOG2 SO T2O Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 22.11.4 Timer 2 Output Mode 4 Biphase Modulator: Timer 2 Modulates the SSI Internal Data Output (SO) to Biphase Code Figure 22-19. Biphase Modulation TOG2 SC 8-bit SR-Data SO T2O 0 Bit 7 0 Data: 00110101 0 1 1 0 1 0 1 Bit 0 0 1 1 0 1 0 1 52 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 22.11.5 Timer 2 Output Mode 5 Manchester Modulator: Timer 2 Modulates the SSI internal data output (SO) to Manchester code Figure 22-20. Manchester Modulation TOG2 SC 8-bit SR-Data SO T2O 0 0 Bit 7 0 0 1 1 0 1 0 1 Bit 0 1 1 0 1 0 1 Bit 0 Bit 7 Data: 00110101 22.11.6 Timer 2 Output Mode 7 In this mode the timer overflow defines the period and the compare register defines the duty cycle. During one period only the first compare match occurrence is used to toggle the timer output flip-flop, until the overflow all further compare match are ignored. This avoids the situation that changing the compare register causes the occurrence of several compare match during one period. The resolution at the pulse-width modulation Timer 2 mode 1 is 12-bit and all other Timer 2 modes are 8-bit. PWM Mode: Pulse-width modulation output on Timer 2 output pin (T2O) Figure 22-21. PWM Modulation Input clock Counter 2/2 T2R 0 0 50 255 0 100 255 0 150 255 0 50 255 0 100 Counter 2/2 CM2 OVF2 INT4 T2O T1 T load the next compare value T2CO2=150 load load T2 T T3 T T1 T T2 T 22.12 Timer 2 Registers Timer 2 has 6 control registers to configure the timer mode, the time interval, the input clock and its output function. All registers are indirectly addressed using extended addressing as described in section "Addressing Peripherals" on page 32. The alternate functions of the Ports BP41 or BP42 must be selected with the Port 4 control register P4CR, if one of the Timer 2 modes require an input at T2I/BP41 or an output at T2O/BP42. 53 4552H-4BMCU-07/07 22.12.1 Timer 2 Control Register (T2C) Address: "7"hex - Subaddress: "0"hex Bit 3 T2CS1 Bit 2 T2CS0 Bit 1 T2TS Bit 0 T2R Reset value: 0000b T2CS1 T2CS0 Timer 2 Clock Select bit 1 Timer 2 Clock Select bit 0 Table 22-7. T2CS1 0 0 1 1 Timer 2 Clock Select Bits T2CS0 0 1 0 1 Input Clock (CL 2/1) of Counter Stage 2/1 System clock (SYSCL) Output signal of Timer 1 (T1OUT) Internal shift clock of SSI (SCL) Output signal of Timer 3 (TOG3) T2TS Timer 2 Toggle with Start T2TS = 0, the output flip-flop of Timer 2 is not toggled with the timer start T2TS = 1, the output flip-flop of Timer 2 is toggled when the timer is started with T2R Timer 2 Run T2R = 0, Timer 2 stop and reset T2R = 1, Timer 2 run T2R 22.12.2 Timer 2 Mode Register 1 (T2M1) Address: "7"hex - Subaddress: "1"hex Bit 3 T2D1 Bit 2 T2D0 Bit 1 T2MS1 Bit 0 T2MS0 Reset value: 1111b T2D1 T2D0 Timer 2 Duty cycle bit 1 Timer 2 Duty cycle bit 0 Table 22-8. T2D1 1 1 0 0 Timer 2 Duty Cycle Bits T2D0 1 0 1 0 Function of Duty Cycle Generator (DCG) Bypassed (DCGO0) Duty cycle 1/1 (DCGO1) Duty cycle 1/2 (DCGO2) Duty cycle 1/3 (DCGO3) Additional Divider Effect /1 /2 /3 /4 T2MS1 T2MS0 Timer 2 Mode Select bit 1 Timer 2 Mode Select bit 0 54 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 Table 22-9. Mode 1 Timer 2 Mode Select Bits T2MS0 1 Clock Output (POUT) 4-bit counter overflow (OVF1) Timer 2 Modes 12-bit compare counter; the DCG has to be bypassed in this mode 8-bit compare counter with 4-bit programmable prescaler and duty cycle generator 8-bit compare counter clocked by SYSCL or the external clock input T2I, 4-bit prescaler run, the counter 2/1 starts after writing mode 3 8-bit compare counter clocked by SYSCL or the external clock input T2I, 4-bit prescaler stop and resets T2MS1 1 2 1 0 4-bit compare output (CM1) 3 0 1 4-bit compare output (CM1) 4 0 0 4-bit compare output (CM1) 22.12.3 Duty Cycle Generator The duty cycle generator generates duty cycles of 25%, 33% or 50%. The frequency at the duty cycle generator output depends on the duty cycle and the Timer 2 prescaler setting. The DCG-stage can also be used as additional programmable prescaler for Timer 2. Figure 22-22. DCG Output Signals DCGIN DCGO0 DCGO1 DCGO2 DCGO3 22.12.4 Timer 2 Mode Register 2 (T2M2) Address: "7"hex - Subaddress: "2"hex Bit 3 T2TOP Bit 2 T2OS2 Bit 1 T2OS1 Bit 0 T2OS0 Reset value: 1111b T2TOP Timer 2 Toggle Output Preset This bit allows the programmer to preset the Timer 2 output T2O. T2TOP = 0, resets the toggle outputs with the write cycle (M2 = 0) T2TOP = 1, sets toggle outputs with the write cycle (M2 = 1) Note: If T2R = 1, no output preset is possible Timer 2 Output Select bit 2 Timer 2 Output Select bit 1 Timer 2 Output Select bit 0 T2OS2 T2OS1 T2OS0 55 4552H-4BMCU-07/07 Table 22-10. Timer 2 Output Select Bits Output Mode 1 2 T2OS2 1 1 T2OS1 1 1 T2OS0 1 0 Clock Output Toggle mode: a Timer 2 compare match toggles the output flip-flop (M2) -> T2O Duty cycle burst generator 1: the DCG output signal (DCG0) is given to the output and gated by the output flip-flop (M2) Duty cycle burst generator 2: the DCG output signal (DCGO) is given to the output and gated by the SSI internal data output (SO) Biphase modulator: Timer 2 modulates the SSI internal data output (SO) to Biphase code Manchester modulator: Timer 2 modulates the SSI internal data output (SO) to Manchester code SSI output: T2O is used directly as SSI internal data output (SO) PWM mode: an 8-/12-bit PWM mode Not allowed 3 1 0 1 4 5 6 7 8 1 0 0 0 0 0 1 1 0 0 0 1 0 1 0 If one of these output modes is used the T2O alternate function of Port 4 must also be activated. 22.12.5 Timer 2 Compare and Compare Mode Registers Timer 2 has two separate compare registers, T2CO1 for the 4-bit stage and T2CO2 for the 8-bit stage of Timer 2. The timer compares the contents of the compare register current counter value and if it matches it generates an output signal. Dependent on the timer mode, this signal is used to generate a timer interrupt, to toggle the output flip-flop as SSI clock or as a clock for the next counter stage. In the 12-bit timer mode, T2CO1 contains bits 0 to 3 and T2CO2 bits 4 to 11 of the 12-bit compare value. In all other modes, the two compare registers work independently as a 4- and 8-bit compare register. When assigned to the compare register a compare event will be suppressed. 56 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 22.12.6 Timer 2 Compare Mode Register (T2CM) Address: "7"hex - Subaddress: "3"hex Bit 3 T2OTM Bit 2 T2CTM Bit 1 T2RM Bit 0 T2IM Reset value: 0000b T2OTM Timer 2 Overflow Toggle Mask bit T2OTM = 0, disable overflow toggle T2OTM = 1, enable overflow toggle, a counter overflow (OVF2) toggles output flip-flop (TOG2). If the T2OTM bit is set, only a counter overflow can generate an interrupt except on the Timer 2 output mode 7. Timer 2 Compare Toggle Mask bit T2CTM = 0, disable compare toggle T2CTM = 1, enable compare toggle, a match of the counter with the compare register toggles output flip-flop (TOG2). In Timer 2 output mode 7 and when the T2CTM bit is set, only a match of the counter with the compare register can generate an interrupt. Timer 2 Reset Mask bit T2RM = 0, disable counter reset T2RM = 1, enable counter reset, a match of the counter with the compare register resets the counter Timer 2 Interrupt Mask bit T2IM = 0, disable Timer 2 interrupt T2IM = 1, enable Timer 2 interrupt T2CTM T2RM T2IM Table 22-11. Timer 2 Toggle Mask Bits Timer 2 Output Mode 1, 2, 3, 4, 5 and 6 1, 2, 3, 4, 5 and 6 7 T2OTM 0 1 x T2CTM x x 1 Timer 2 Interrupt Source Compare match (CM2) Overflow (OVF2) Compare match (CM2) 22.12.7 Timer 2 COmpare Register 1 (T2CO1) Address: "7"hex - Subaddress: "4"hex Write cycle Bit 3 Bit 2 Bit 1 Bit 0 Reset value: 1111b In prescaler mode the clock is bypassed if the compare register T2CO1 contains 0. 22.12.8 Timer 2 COmpare Register 2 (T2CO2) Byte Write Address: "7"hex - Subaddress: "5"hex First write cycle Second write cycle Bit 3 Bit 7 Bit 2 Bit 6 Bit 1 Bit 5 Bit 0 Bit 4 Reset value: 1111b Reset value: 1111b 57 4552H-4BMCU-07/07 23. Timer 3 23.1 Features * * * * * * * * * * * Figure 23-1. Timer 3 TOG2 T3I T3EIM Two Compare Registers Capture Register Edge Sensitive Input with Zero Cross Detection Capability Trigger and Single Action Modes Output Control Modes Automatically Modulation and Demodulation Modes FSK Modulation Pulse Width Modulation (PWM) Manchester Demodulation Together with SSI Biphase Demodulation Together with SSI Pulse-width Demodulation Together with SSI Control INT5 Capture register D NQ CL3 T3SM1 T3RM1 T3IM1 T3TM1 : T3M1 8-bit counter RES CM31 8-bit comparator Control C31 C32 CM32 TOG3 Compare register 1 NQ D T3SM2 T3RM2 T3IM2 T3TM2 : T3M2 Compare register 2 Timer 3 consists of an 8-bit up-counter with two compare registers and one capture register. The timer can be used as event counter, timer and signal generator. Its output can be programmed as modulator and demodulator for the serial interface. The two compare registers enable various modes of signal generation, modulation and demo-dulation. The counter can be driven by internal and external clock sources. For external clock sources, it has a programmable edge-sensitive input which can be used as counter input, capture signal input or trigger input. This timer input is synchronized with SYSCL. Therefore, in the power-down mode SLEEP (CPU core -> sleep and OSC-Stop -> yes), this timer input is stopped too. The counter is readable via its capture register while it is running. In capture mode, the counter value can be captured by a programmable capture event from the Timer 3 input or Timer 2 output. 58 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 A special feature of this timer is the trigger- and single-action mode. In trigger mode, the counter starts counting triggered by the external signal at its input. In single-action mode, the counter counts only one time up to the programmed compare match event. These modes are very useful for modulation, demodulation, signal generation, signal measurement and phase controlling. For phase controlling, the timer input is protected against negative voltages and has zero-cross detection capability. Timer 3 has a modulator output stage and input functions for demodulation. As modulator it works together with Timer 2 or the serial interface. When the shift register is used for modulation the data shifted out of the register is encoded bitwise. In all demodulation modes, the decoded data bits are shifted automatically into the shift register. 23.2 Timer/Counter Modes Timer 3 has 6 timer modes and 6 modulator/demodulator modes. The mode is set via the Timer 3 Mode Register T3M. In all these modes, the compare register and the compare-mode register belonging to it define the counter value for a compare match and the action of a compare match. A match of the current counter value with the content of one compare register triggers a counter reset, a Timer 3 interrupt or the toggling of the output flip-flop. The compare mode registers T3M1 and T3M2 contain the mask bits for enabling or disabling these actions. The counter can also be enabled to execute single actions with one or both compare registers. If this mode is set the corresponding compare match event is generated only once after the counter start. Most of the timer modes use their compare registers alternately. After the start has been activated, the first comparison is carried out via the compare register 1, the second is carried out via the compare register 2, the third is carried out again via the compare register 1 and so on. This makes it easy to generate signals with constant periods and variable duty cycle or to generate signals with variable pulse and space widths. If single-action mode is set for one compare register, the comparison is always carried out after the first cycle via the other compare register. The counter can be started and stopped via the control register T3C. This register also controls the initial level of the output before start. T3C contains the interrupt mask for a T3I input interrupt. Via the Timer 3 clock-select register, the internal or external clock source can be selected. This register selects also the active edge of the external input. An edge at the external input T3I can generate also an interrupt if the T3EIM bit is set and the Timer 3 is stopped (T3R = 0) in the T3C register. 59 4552H-4BMCU-07/07 Figure 23-2. Counter 3 Stage TOG2 T3I T3EIM Control INT5 Capture register D NQ CL3 T3SM1 T3RM1 T3IM1 T3TM1 : T3M1 8-bit counter RES CM31 8-bit comparator Control C31 C32 CM32 TOG3 Compare register 1 NQ D T3SM2 T3RM2 T3IM2 T3TM2 : T3M2 Compare register 2 The status of the timer as well as the occurrence of a compare match or an edge detect of the input signal is indicated by the status register T2ST. This allows identification of the interrupt source because all these events share only one timer interrupt. Timer 3 compares data values. The Timer 3 has two 8-bit compare registers (T3CO1, T3CO2). The compare data value can be m for each of the Timer 3 compare registers. The compare data value for the compare registers is: 23.2.1 m = x +1 0 x 255 Timer 3 - Mode 1: Timer/Counter The selected clock from an internal or external source increments the 8-bit counter. In this mode, the timer can be used as event counter for external clocks at T3I or as timer for generating interrupts and pulses at T3O. The counter value can be read by the software via the capture register. Figure 23-3. Counter Reset with Each Compare Match T3R 0 0 0 1 2 3 0 1 2 3 4 5 0 1 2 3 0 1 2 3 Counter 3 CM31 CM32 INT5 T3O 60 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 Figure 23-4. Counter Reset with Compare Register 2 and Toggle with Start CL3 T3R 0 0 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 Counter 3 CM31 CM32 INT5 T3O T3O Toggle by start Figure 23-5. Single Action of Compare Register 1 T3R 0 0 1 2 3 4 5 6 7 8 9 10 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 Counter 3 CM31 CM32 T3O Toggle by start 23.2.2 Timer 3 - Mode 2: Timer/Counter, External Trigger Restart and External Capture (with T3I Input) The counter is driven by an internal clock source. After starting with T3R, the first edge from the external input T3I starts the counter. The following edges at T3I load the current counter value into the capture register, reset the counter and restart it. The edge can be selected by the programmable edge decoder of the timer input stage. If single-action mode is activated for one or both compare registers the trigger signal restarts the single action. Figure 23-6. Externally Triggered Counter Reset and Start Combined with Single-action Mode T3R 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 0 1 2 X X X 0 1 2 3 4 5 6 7 8 9 10 0 1 2 X X X X Counter 3 T3EX CM31 CM32 T3O 61 4552H-4BMCU-07/07 23.2.3 Timer 3 - Mode 3: Timer/Counter, Internal Trigger Restart and Internal Capture (with TOG2) The counter is driven by an internal or external (T3I) clock source. The output toggle signal of Timer 2 resets the counter. The counter value before the reset is saved in the capture register. If single-action mode is activated for one or both compare registers, the trigger signal restarts the single actions. This mode can be used for frequency measurements or as event counter with time gate (see section "Combination Mode 10: Frequency Measurement or Event Counter with Time Gate" on page 91). Figure 23-7. Event Counter with Time Gate T3R T3I Counter 3 TOG2 T3CPRegister Capture value = 0 Capture value = 11 Cap. val. = 4 0 0 1 2 3 4 5 6 7 8 9 10 11 01 2 3 4 012 23.2.4 Timer 3 - Mode 4: Timer/Counter The timer runs as timer/counter in mode 1, but its output T3O is used as output for the Timer 2 output signal. 23.2.5 Timer 3 - Mode 5: Timer/Counter, External Trigger Restart and External Capture (with T3I Input) The Timer 3 runs as timer/counter in mode 2, but its output T3O is used as output for the Timer 2 output signal. 62 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 23.3 23.3.1 Timer 3 Modulator/Demodulator Modes Timer 3 - Mode 6: Carrier Frequency Burst Modulation Controlled by Timer 2 Output Toggle Flip-Flop (M2) The Timer 3 counter is driven by an internal or external clock source. Its compare- and compare mode registers must be programmed to generate the carrier frequency via the output toggle flip-flop. The output toggle flip-flop of Timer 2 is used to enable or disable the Timer 3 output. Timer 2 can be driven by the toggle output signal of Timer 3 or any other clock source (see section "Combination Mode 11: Burst Modulation 1" on page 92). Timer 3 - Mode 7: Carrier Frequency Burst Modulation Controlled by SSI Internal Output (SO) The Timer 3 counter is driven by an internal or external clock source. Its compare- and compare mode registers must be programmed to generate the carrier frequency via the output toggle flip-flop. The output (SO) of the SSI is used to enable or disable the Timer 3 output. The SSI should be supplied with the toggle signal of Timer 2 (see section "Combination Mode 12: Burst Modulation 2" on page 94). Timer 3 - Mode 8: FSK Modulation with Shift Register Data (SO) The two compare registers are used for generating two different time intervals. The SSI internal data output (SO) selects which compare register is used for the output frequency generation. A "0" level at the SSI data output enables the compare register 1. A "1" level enables compare register 2. The compare- and compare-mode registers must be programmed to generate the two frequencies via the output toggle flip-flop. The SSI can be supplied with the toggle signal of Timer 2. The Timer 3 counter is driven by an internal or external clock source. The Timer 2 counter is driven by the Counter 3 (TOG3) (see section "Combination Mode 13: FSK Modulation" on page 94). Figure 23-8. FSK Modulation T3R 0123401234012340120120120120120120120123401 23.3.2 23.3.3 Counter 3 CM31 CM32 SO T3O 0 1 0 63 4552H-4BMCU-07/07 23.3.4 Timer 3 - Mode 9: Pulse-width Modulation with the Shift Register The two compare registers are used for generating two different time intervals. The SSI internal data output (SO) selects which compare register is used for the output pulse generation. In this mode both compare- and compare-mode registers must be programmed for generating the two pulse widths. It is also useful to enable the single-action mode for extreme duty cycles. Timer 2 is used as baudrate generator and for the trigger restart of Timer 3. The SSI must be supplied with a toggle signal of Timer 2. The counter is driven by an internal or external clock source (see section "Combination Mode 7: Pulse-width Modulation (PWM)" on page 88). Figure 23-9. Pulse-width Modulation TOG2 SIR 0 1 0 1 SO SCO T3R Counter 3 CM31 CM32 T3O 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 1011121314150 1 2 3 4 5 6 7 8 9 101112131415 0 1 2 3 4 23.3.5 Timer 3 - Mode 10: Manchester Demodulation/ Pulse-width Demodulation For Manchester demodulation, the edge detection stage must be programmed to detect each edge at the input. These edges are evaluated by the demodulator stage. The timer stage is used to generate the shift clock for the SSI. The compare register 1 match event defines the correct moment for shifting the state from the input T3I as the decoded bit into shift register - after that the demodulator waits for the next edge to synchronize the timer by a reset for the next bit. The compare register 2 can also be used to detect a time-out error and handle it with an interrupt routine (see section "Combination Mode 8: Manchester Demodulation/ Pulse-width Demodulation" on page 89). Figure 23-10. Manchester Demodulation Timer 3 mode T3I T3EX SI CM31=SCI SR-DATA 1 BIT 0 1 BIT 1 1 BIT 2 0 BIT 3 0 BIT 4 1 BIT 5 1 BIT 6 0 Synchronize 1 0 1 1 Manchester demodulation mode 1 0 0 1 1 0 64 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 23.3.6 Timer 3 - Mode 11: Biphase Demodulation In the Biphase demodulation mode, the timer operates like in Manchester demodulation mode. The difference is that the bits are decoded via a toggle flip-flop. This flip-flop samples the edge in the middle of the bitframe and the compare register 1 match event shifts the toggle flip-flop output into shift register (see section "Combination Mode 9: Biphase Demodulation" on page 90). Figure 23-11. Biphase Demodulation Timer 3 mode T3I T3EX Q1=SI CM31=SCI Reset Counter 3 SR-DATA 0 BIT 0 1 BIT 1 1 BIT 2 0 BIT 3 1 BIT 4 0 BIT 5 1 BIT 6 0 Synchronize 0 0 1 1 Biphase demodulation mode 0 1 0 1 0 23.3.7 Timer 3 - Mode 12: Timer/Counter with External Capture Mode (T3I) The counter is driven by an internal clock source and an edge at the external input T3I loads the counter value into the capture register. The edge can be selected with the programmable edge detector of the timer input stage. This mode can be used for signal and pulse measurements. Figure 23-12. External Capture Mode T3R T3I Counter 3 T3CPRegister 0 0 1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132333435363738394041 Capture value = X Capture value = 17 Capture value = 35 65 4552H-4BMCU-07/07 23.4 Timer 3 Modulator for Carrier Frequency Burst Modulation If the output stage operates as pulse-width modulator for the shift register, the output can be stopped with stage 1 of Timer 2. For this task, the timer mode 3 must be used and the prescaler must be supplied by the internal shift clock of the shift register. The modulator can be started with the start of the shift register (SIR = 0) and stopped either by a shift register stop (SIR = 1) or compare match event of stage 1 of Timer 2. For this task, the Timer 2 must be used in mode 3 and the prescaler stage must be supplied by the internal shift clock of the shift register. Figure 23-13. Modulator 3 0 TOG3 Set T3 Res 2 MUX T3O M3 1 T3TOP SO M2 Timer 3 Mode 6 7 9 other T3O MUX 1 MUX 2 MUX 3 MUX 0 3 SSI/ Control OMSK T3M 23.5 Timer 3 Demodulator for Biphase, Manchester and Pulse-width-modulated Signals The demodulator stage of Timer 3 can be used to decode Biphase, Manchester and pulse-width-coded signals. Figure 23-14. Timer 3 Demodulator 3 T3M T3I Demodulator 3 T3EX Res SCI SI CM31 Counter 3 Reset Counter 3 Control 66 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 23.6 23.6.1 Timer 3 Registers Timer 3 Mode Register (T3M) Address: "B"hex - Subaddress: "0"hex Bit 3 T3M3 Bit 2 T3M2 Bit 1 T3M1 Bit 0 T3M0 Reset value: 1111b T3M3 T3M2 T3M1 T3M0 Timer 3 Mode select bit 3 Timer 3 Mode select bit 2 Timer 3 Mode select bit 1 Timer 3 Mode select bit 0 Table 23-1. Mode 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Note: 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Timer 3 Mode Select Bits T3M2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 T3M1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 T3M0 Timer 3 Modes 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Timer/counter with a read access Timer/counter, external capture and external trigger restart mode (T3I) Timer/counter, internal capture and internal trigger restart mode (TOG2) Timer/counter mode 1 without output (T2O -> T3O) Timer/counter mode 2 without output (T2O -> T3O) Burst modulation with Timer 2 (M2) Burst modulation with shift register (SO) FSK modulation with shift register (SO) Pulse-width modulation with shift register (SO) and Timer 2 (TOG2), internal trigger restart (SCO) -> counter reset Manchester demodulation/pulse-width demodulation(1) (T2O -> T3O) Biphase demodulation (T2O -> T3O) Timer/counter with external capture mode (T3I) Not allowed Not allowed Not allowed Not allowed T3M3 1. In this mode, the SSI can be used only as demodulator (8-bit NRZ rising edge). All other SSI modes are not allowed. 67 4552H-4BMCU-07/07 23.6.2 Timer 3 Control Register 1 (T3C) Write Primary register address: "C"hex - Write Bit 3 Write T3EIM Bit 2 T3TOP Bit 1 T3TS Bit 0 T3R Reset value: 0000b T3EIM Timer 3 Edge Interrupt Mask T3EIM = 0, disables the interrupt when an edge event for Timer 3 occurs (T3I) T3EIM = 1, enables the interrupt when an edge event for Timer 3 occurs (T3I) Timer 3 Toggle Output Preset T3TOP = 0, sets toggle output (M3) to "0" ............. .......T3TOP = 1, sets toggle output (M3) to "1" ............. .......Note: If T3R = 1, no output preset is possible Timer 3 Toggle with Start . T3TS = 0, Timer 3 output is not toggled during the start ...... ...... T3TS = 1, Timer 3 output is toggled if started with T3R Timer 3 Run ...... ...... T3R = 0, Timer 3 stop and reset ...... ...... T3R = 1, Timer 3 run T3TOP T3TS T3R 23.6.3 Timer 3 Status Register 1 (T3ST) Read Primary register address: "C"hex - Read Bit 3 Read --Bit 2 T3ED Bit 1 T3C2 Bit 0 T3C1 Reset value: x000b T3ED T3C2 T3C1 Note: Timer 3 Edge Detect This bit will be set by the edge-detect logic of Timer 3 input (T3I) Timer 3 Compare 2 This bit will be set when a match occurs between Counter 3 and T3CO2 Timer 3 Compare 1 This bit will be set when a match occurs between Counter 3 and T3CO1 The status bits T3C1, T3C2 and T3ED will be reset after a READ access to T3ST. 68 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 23.6.4 Timer 3 Clock Select Register (T3CS) Address: "B"hex - Subaddress: "1"hex Bit 3 T3CS T3E1 Bit 2 T3E0 Bit 1 T3CS1 Bit 0 T3CS0 Reset value: 1111b T3E1 T3E0 Timer 3 Edge select bit 1 Timer 3 Edge select bit 0 Table 23-2. T3E1 1 1 0 0 Timer 3 Edge Select Bits T3E0 1 0 1 0 Timer 3 Input Edge Select (T3I) - Positive edge at T3I pin Negative edge at T3I pin Each edge at T3I pin T3CS1 Timer 3 Clock Source select bit 1 T3CS0 Timer 3 Clock Source select bit 0 Table 23-3. T3CS1 1 1 0 0 Timer 3 Clock Select Bits TCS0 1 0 1 0 Counter 3 Input Signal (CL3) System clock (SYSCL) Output signal of Timer 2 (POUT) Output signal of Timer 1 (T1OUT) External input signal from T3I edge detect 23.6.5 Timer 3 Compare- and Compare-mode Register Timer 3 has two separate compare registers T3CO1 and T3CO2 for the 8-bit stage of Timer 3. The timer compares the content of the compare register with the current counter value. If both match, it generates a signal. This signal can be used for the counter reset, to generate a timer interrupt, for toggling the output flip-flop, as SSI clock or as clock for the next counter stage. For each compare register, a compare-mode register exists. These registers contain mask bits to enable or disable the generation of an interrupt, a counter reset, or an output toggling with the occurrence of a compare match of the corresponding compare register. The mask bits for activating the single-action mode can also be located in the compare mode registers. When assigned to the compare register a compare event will be suppressed. 69 4552H-4BMCU-07/07 23.6.6 Timer 3 Compare-Mode Register 1 (T3CM1) Address: "B"hex - Subaddress: "2"hex Bit 3 T3CM1 T3SM1 Bit 2 T3TM1 Bit 1 T3RM1 Bit 0 T3IM1 Reset value: 0000b T3SM1 Timer 3 Single action Mask bit 1 T3SM1 = 0, disables single-action compare mode T3SM1 = 1, enables single-compare mode. After this bit is set, the compare register (T3CO1) is used until the next compare match. Timer 3 compare Toggle action Mask bit 1 T3TM1 = 0, disables compare toggle T3TM1 = 1, enables compare toggle. A match of Counter 3 with the compare register (T3CO1) toggles the output flip-flop (TOG3). Timer 3 Reset Mask bit 1 T3RM1 = 0, disables counter reset T3RM1 = 1, enables counter reset. A match of Counter 3 with the compare register (T3CO1) resets the Counter 3. Timer 3 Interrupt Mask bit 1 T3RM1 = 0, disables Timer 3 interrupt for T3CO1 register. T3RM1 = 1, enables Timer 3 interrupt for T3CO1 register. T3TM1 T3RM1 T3IM1 T3CM1 contains the mask bits for the match event of the Counter 3 compare register 1. 23.6.7 Timer 3 Compare Mode Register 2 (T3CM2) Address: "B"hex - Subaddress: "3"hex Bit 3 T3CM2 T3SM2 Bit 2 T3TM2 Bit 1 T3RM2 Bit 0 T3IM2 Reset value: 0000b T3SM2 Timer 3 Single action Mask bit 2 T3SM2 = 0, disables single-action compare mode T3SM2 = 1, enables single-compare mode. After this bit is set, the compare register (T3CO2) is used until the next compare match. Timer 3 compare Toggle action Mask bit 2 T3TM2 = 0, disables compare toggle T3TM2 = 1, enables compare toggle. A match of Counter 3 with the compare register (T3CO2) toggles the output flip-flop (TOG3). Timer 3 Reset Mask bit 2 T3RM2 = 0, disables counter reset T3RM2 = 1, enables counter reset. A match of Counter 3 with the compare register (T3CO2) resets the Counter 3. Timer 3 Interrupt Mask bit 2 T3RM2 = 0, disables Timer 3 interrupt for T3CO2 register. T3RM2 = 1, enables Timer 3 interrupt for T3CO2 register. T3TM2 T3RM2 T3IM2 T3CM2 contains the mask bits for the match event of Counter 3 compare register 2. 70 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 The compare registers and corresponding counter reset masks can be used to program the counter time intervals and the toggle masks can be used to program output signal. The single-action mask can also be used in this mode. It starts operating after the timer started with T3R. 23.6.8 Timer 3 COmpare Register 1 (T3CO1) Byte Write Address: "B"hex - Subaddress: "4"hex High Nibble Second write cycle Bit 7 Bit 6 Bit 5 Bit 4 Reset value: 1111b Low Nibble First write cycle Bit 3 Bit 2 Bit 15 Bit 0 Reset value: 1111b 23.6.9 Timer 3 COmpare Register 2 (T3CO2) Byte Write Address: "B"hex - Subaddress: "5"hex High Nibble Second write cycle Bit 7 Bit 6 Bit 5 Bit 4 Reset value: 1111b Low Nibble First write cycle Bit 3 Bit 2 Bit 15 Bit 0 Reset value: 1111b 23.7 Timer 3 Capture Register The counter content can be read via the capture register. There are two ways to use the capture register. In mode 1 and mode 4, it is possible to read the current counter value directly out of the capture register. In the capture modes 2, 3, 5 and 12, a capture event like an edge at the Timer 3 input or a signal from Timer 2 stores the current counter value into the capture register. This counter value can be read from the capture register. 23.7.1 Timer 3 CaPture Register (T3CP) Byte Read Address: "B"hex - Subaddress: "4"hex High Nibble First read cycle Bit 7 Bit 6 Bit 5 Bit 4 Reset value: xxxxb Low Nibble Second read cycle Bit 3 Bit 2 Bit 15 Bit 0 Reset value: xxxxb 71 4552H-4BMCU-07/07 23.8 23.8.1 Synchronous Serial Interface (SSI) SSI Features - 2- and 3-wire NRZ - 2-wire multi-chip link mode (MCL), additional internal 2-wire link for multi-chip packaging solutions * With Timer 2 - Biphase modulation - Manchester modulation - Pulse-width demodulation - Burst modulation * With Timer 3 - Pulse-width modulation (PWM) - FSK modulation - Biphase demodulation - Manchester demodulation - Pulse-width demodulation - Pulse position demodulation 23.8.2 SSI Peripheral Configuration The synchronous serial interface (SSI) can be used either for serial communication with external devices such as EEPROMs, shift registers, display drivers, other microcon-trollers, or as a means for generating and capturing on-chip serial streams of data. External data communication takes place via the Port 4 (BP4),a multi-functional port which can be software configured by writing the appropriate control word into the P4CR register. The SSI can be configured in any of the following ways: 1. 2-wire external interface for bi-directional data communication with one data terminal and one shift clock. The SSI uses the Port BP43 as a bi-directional serial data line (SD) and BP40 as shift clock line (SC). 2. 3-wire external interface for simultaneous input and output of serial data, with a serial input data terminal (SI), a serial output data terminal (SO) and a shift clock (SC). The SSI uses BP40 as shift clock (SC), while the serial data input (SI) is applied to BP43 (configured in P4CR as input.). Serial output data (SO) in this case is passed through to BP42 (configured in P4CR to T2O) via the Timer 2 output stage (T2M2 configured in mode 6). 3. Timer/SSI combined modes - the SSI used together with Timer 2 or Timer 3 is capable of performing a variety of data modulation and demodulation functions (see section Timer). The modulating data is converted by the SSI into a continuous serial stream of data which is in turn modulated in one of the timer functional blocks. Serial demodulated data can be serially captured in the SSI and read by the controller. In the Timer 3 modes 10 and 11 (demodulation modes) the SSI can only be used as demodulator. 72 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 4. Internal Multi-Chip Link pads (MCL) - the SSI can also be used as an interchip data interface for use in single package multi-chip modules or hybrids. For such applications, the SSI is provided with two dedicated pads (MCL_SD and MCL_SC) which act as a two-wire chip-to-chip link. The internal MCL can be activated by the MCL control bit. Should these MCL pads be used by the SSI, the standard SD and SC pins are not required and the corresponding Port 4 ports are available as conventional data ports. Figure 23-15. Block Diagram of the Synchronous Serial Interface I/O-bus Timer 2 / Timer 3 SIC1 SIC2 SISC SO Control SC SSI-Control Output SO /2 Shift_CL SI SCI SC MCL_SC INT3 TOG2 POUT T1OUT SYSCL 8-bit Shift Register MSB LSB SI MCL_SD SD STB Transmit Buffer I/O-bus SRB Receive Buffer 23.8.3 General SSI Operation The SSI is comprised essentially of an 8-bit shift register with two associated 8-bit buffers - the receive buffer (SRB) for capturing the incoming serial data and a transmit buffer (STB) for intermediate storage of data to be serially output. Both buffers are directly accessable by software. Transferring the parallel buffer data into and out of the shift register is controlled automatically by the SSI control, so that both single byte transfers or continuous bit streams can be supported. The SSI can generate the shift clock (SC) either from one of several on-chip clock sources or accept an external clock. The external shift clock is output on, or applied to the Port BP40. Selection of an external clock source is performed by the Serial Clock Direction control bit (SCD). In the combinational modes, the required clock is selected by the corresponding timer mode. The SSI can operate in three data transfer modes - synchronous 8-bit shift mode, a 9-bit Multi-Chip Link Mode (MCL), containing 8-bit data and 1-bit acknowledge, and a corresponding 8-bit MCL mode without acknowledge. In both MCL modes the data transmission begins after a valid start condition and ends with a valid stop condition. External SSI clocking is not supported in these modes. The SSI should thus generate and has full control over the shift clock so that it can always be regarded as an MCL Bus Master device. All directional control of the external data port used by the SSI is handled automatically and is dependent on the transmission direction set by the Serial Data Direction (SDD) control bit. This control bit defines whether the SSI is currently operating in Transmit (TX) mode or Receive (RX) mode. 73 4552H-4BMCU-07/07 Serial data is organized in 8-bit telegrams which are shifted with the most significant bit first. In the 9-bit MCL mode, an additional acknowledge bit is appended to the end of the telegram for handshaking purposes (see section "MCL Bus Protocol" on page 77). At the beginning of every telegram, the SSI control loads the transmit buffer into the shift register and proceeds immediately to shift data serially out. At the same time, incoming data is shifted into the shift register input. This incoming data is automatically loaded into the receive buffer when the complete telegram has been received. Thus, data can be simultaneously received and transmitted if required. Before data can be transferred, the SSI must first be activated. This is performed by means of the SSI reset control (SIR) bit. All further operation then depends on the data directional mode (TX/RX) and the present status of the SSI buffer registers shown by the Serial Interface Ready Status Flag (SRDY). This SRDY flag indicates the (empty/full) status of either the transmit buffer (in TX mode), or the receive buffer (in RX mode). The control logic ensures that data shifting is temporarily halted at any time, if the appropriate receive/transmit buffer is not ready (SRDY = 0). The SRDY status will then automatically be set back to `1' and data shifting resumed as soon as the application software loads the new data into the transmit register (in TX mode) or frees the shift register by reading it into the receive buffer (in RX mode). A further activity status (ACT) bit indicates the present status of the serial communication. The ACT bit remains high for the duration of the serial telegram or if MCL stop or start conditions are currently being generated. Both the current SRDY and ACT status can be read in the SSI status register. To deactivate the SSI, the SIR bit must be set high. 23.8.4 8-bit Synchronous Mode Figure 23-16. 8-bit Synchronous Mode SC (Rising edge) SC (Falling edge) DATA 0 Bit 7 SD/TO2 0 Bit 7 Data: 00110101 0 1 1 0 1 0 0 1 1 0 1 0 1 Bit 0 1 Bit 0 In the 8-bit synchronous mode, the SSI can operate as either a 2- or 3-wire interface (see section "SSI Peripheral Configuration" on page 72). The serial data (SD) is received or transmitted in NRZ format, synchronized to either the rising or falling edge of the shift clock (SC). The choice of clock edge is defined by the Serial Mode Control bits (SM0,SM1). It should be noted that the transmission edge refers to the SC clock edge with which the SD changes. To avoid clock skew problems, the incoming serial input data is shifted in with the opposite edge. When used together with one of the timer modulator or demodulator stages, the SSI must be set in the 8-bit synchronous mode 1. In RX mode, as soon as the SSI is activated (SIR = 0), 8 shift clocks are generated and the incoming serial data is shifted into the shift register. This first telegram is automatically transferred into the receive buffer and the SRDY set to 0 indicating that the receive buffer contains 74 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 valid data. At the same time an interrupt (if enabled) is generated. The SSI then continues shifting in the following 8-bit telegram. If, during this time the first telegram has been read by the controller, the second telegram will also be transferred in the same way into the receive buffer and the SSI will continue clocking in the next telegram. Should, however, the first telegram not have been read (SRDY = 1), then the SSI will stop, temporarily holding the second telegram in the shift register until a certain point of time when the controller is able to service the receive buffer. In this way no data is lost or overwritten. Deactivating the SSI (SIR = 1) in mid-telegram will immediately stop the shift clock and latch the present contents of the shift register into the receive buffer. This can be used for clocking in a data telegram of less than 8 bits in length. Care should be taken to read out the final complete 8-bit data telegram of a multiple word message before deactivating the SSI (SIR = 1) and terminating the reception. After termination, the shift register contents will overwrite the receive buffer. Figure 23-17. Example of 8-bit Synchronous Transmit Operation SC msb SD lsb 0 msb lsb msb lsb 0 7654321 765432107654321 tx data 1 SIR tx data 2 tx data 3 SRDY ACT Interrupt (IFN = 0) Interrupt (IFN = 1) Write STB (tx data 1) Write STB (tx data 2) Write STB (tx data 3) Figure 23-18. Example of 8-bit Synchronous Receive Operation SC msb SD lsb msb lsb msb lsb 7654321076543210 rx data 1 rx data 2 765432107654 rx data 3 SIR SRDY ACT Interrupt (IFN = 0) Interrupt (IFN = 1) Read SRB (rx data 1) Read SRB (rx data 2) Read SRB (rx data 3) 75 4552H-4BMCU-07/07 23.8.5 9-bit Shift Mode (MCL) In the 9-bit shift mode, the SSI is able to handle the MCL protocol described below. It always operates as an MCL master device, i.e., SC is always generated and output by the SSI. Both the MCL start and stop conditions are automatically generated whenever the SSI is activated or deactivated by the SIR bit. In accordance with the MCL protocol, the output data is always changed in the clock low phase and shifted in on the high phase. Before activating the SSI (SIR = 0) and commencing an MCL dialog, the appropriate data direction for the first word must be set using the SDD control bit. The state of this bit controls the direction of the data port (BP43 or MCL_SD). Once started, the 8 data bits are, depending on the selected direction, either clocked into or out of the shift register. During the 9th clock period, the port direction is automatically switched over so that the corresponding acknowledge bit can be shifted out or read in. In transmit mode, the acknowledge bit received from the device is captured in the SSI Status Register (TACK) where it can be read by the controller. In receive mode, the state of the acknowledge bit to be returned to the device is predetermined by the SSI Status Register (RACK). Changing the directional mode (TX/RX) should not be performed during the transfer of an MCL telegram. One should wait until the end of the telegram which can be detected using the SSI interrupt (IFN = 1) or by interrogating the ACT status. Once started, a 9-bit telegram will always run to completion and will not be prematurely terminated by the SIR bit. So, if the SIR bit is set to "1" in telegram, the SSI will complete the current transfer and terminate the dialog with an MCL stop condition. Figure 23-19. Example of MCL Transmit Dialog Start SC msb SD lsb msb lsb Stop 76543210A tx data 1 76543210A tx data 2 SRDY ACT Interrupt (IFN = 0) Interrupt (IFN = 1) SIR SDD Write STB (tx data 1) Write STB (tx data 2) 76 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 Figure 23-20. Example of MCL Receive Dialog Start SC msb SD lsb msb lsb Stop 76543210A tx data 1 76543210A rx data 2 SRDY ACT Interrupt (IFN = 0) Interrupt (IFN = 1) SIR SDD Write STB (tx data 1) Read SRB (rx data 2) 23.8.6 8-bit Pseudo MCL Mode In this mode, the SSI exhibits all the typical MCL operational features except for the acknowledge bit which is never expected or transmitted. MCL Bus Protocol The MCL protocol constitutes a simple 2-wire bi-directional communication highway via which devices can communicate control and data information. Although the MCL protocol can support multi-master bus configurations, the SSI in MCL mode is intended for use purely as a master controller on a single master bus system. So all reference to multiple bus control and bus contention will be omitted at this point. All data is packaged into 8-bit telegrams plus a trailing handshaking or acknowledge bit. Normally the communication channel is opened with a so-called start condition, which initializes all devices connected to the bus. This is then followed by a data telegram, transmitted by the master controller device. This telegram usually contains an 8-bit address code to activate a single slave device connected onto the MCL bus. Each slave receives this address and compares it with its own unique address. The addressed slave device, if ready to receive data, will respond by pulling the SD line low during the 9th clock pulse. This represents a so-called MCL acknowledge. The controller detecting this affirmative acknowledge then opens a connection to the required slave. Data can then be passed back and forth by the master controller, each 8-bit telegram being acknowledged by the respective recipient. The communication is finally closed by the master device and the slave device put back into standby by applying a stop condition onto the bus. 23.8.7 77 4552H-4BMCU-07/07 Figure 23-21. MCL Bus Protocol 1 (1) SC (2) (4) (4) (3) (1) SD Start condition Data valid Data change Data valid Stop condition Bus not busy (1) Start data transfer (2) Stop data transfer (3) Data valid (4) Both data and clock lines remain HIGH. A HIGH to LOW transition of the SD line while the clock (SC) is HIGH defines a START condition. A LOW to HIGH transition of the SD line while the clock (SC) is HIGH defines a STOP condition. The state of the data line represents valid data when, after START condition, the data line is stable for the duration of the HIGH period of the clock signal. All address and data words are serially transmitted to and from the device in eight-bit words. The receiving device returns a zero on the data line during the ninth clock cycle to acknowledge word receipt. Acknowledge Figure 23-22. MCL Bus Protocol 2 SC 1 n 8 9 SD Start 1st Bit 8th Bit ACK Stop 23.8.8 SSI Interrupt The SSI interrupt INT3 can be generated either by an SSI buffer register status (i.e., transmit buffer empty or receive buffer full), the end of SSI data telegram or on the falling edge of the SC/SD pins on Port 4 (see section "Port 4 Control Register (P4CR) Byte Write" on page 40). SSI interrupt selection is performed by the Interrupt FunctioN control bit (IFN). The SSI interrupt is usually used to synchronize the software control of the SSI and inform the controller of the present SSI status. The Port 4 interrupts can be used together with the SSI or, if the SSI itself is not required, as additional external interrupt sources. In either case this interrupt is capable of waking the controller out of sleep mode. To enable and select the SSI relevant interrupts use the SSI interrupt mask (SIM) and the Interrupt Function (IFN) while the Port 4 interrupts are enabled by setting appropriate control bits in P4CR register. 78 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 23.8.9 Modulation and Demodulation If the shift register is used together with Timer 2 or Timer 3 for modulation or demodulation purposes, the 8-bit synchronous mode must be used. In this case, the unused Port 4 pins can be used as conventional bi-directional ports. The modulation and demodulation stages, if enabled, operate as soon as the SSI is activated (SIR = 0) and cease when deactivated (SIR = 1). Due to the byte-orientated data control, the SSI (when running normally) generates serial bit streams which are submultiples of 8 bits. An SSI output masking (OMSK) function permits; however, the generation of bit streams of any length. The OMSK signal is derived indirectly from the 4-bit prescaler of the Timer 2 and masks out a programmable number of unrequired trailing data bits during the shifting out of the final data word in the bit stream. The number of non-masked data bits is defined by the value pre-programmed in the prescaler compare register. To use output masking, the modulator stop mode bit (MSM) must be set to "0" before programming the final data word into the SSI transmit buffer. This in turn, enables shift clocks to the prescaler when this final word is shifted out. On reaching the compare value, the prescaler triggers the OMSK signal and all following data bits are blanked. 23.8.10 Internal 2-wire Multi-chip Link Two additional on-chip pads (MCL_SC and MCL_SD) for the SC and the SD line can be used as chip-to-chip link for multi-chip applications. These pads can be activated by setting the MCL-bit in the SISC-register. Figure 23-23. Multi-chip Link U505M SCL SDA Multi chip link MCL_SC V DD BP40/SC MCL_SD V SS BP43/SD Microcontroller BP10 BP13 Figure 23-24. SSI Output Masking Function CL2/1 SCL Compare 2/1 CM1 OMSK Control SC SSI-control Output TOG2 POUT T1OUT SYSCL SO /2 Shift_CL MSB 8-bit shift register SI LSB SO 4-bit counter 2/1 Timer 2 79 4552H-4BMCU-07/07 23.9 23.9.1 Serial Interface Registers Serial Interface Control Register 1 (SIC1) Auxiliary register address: "9"hex Bit 3 SIR Bit 2 SCD Bit 1 SCS1 Bit 0 SCS0 Reset value: 1111b SIR Serial Interface Reset SIR = 1, SSI inactive SIR = 0, SSI active Serial Clock Direction SCD = 1, SC line used as output SCD = 0, SC line used as input This bit has to be set to "1" during the MCL mode and the Timer 3 mode 10 or 11 SCD Note: SCS1 SCS0 Note: Serial Clock source Select bit 1 Serial Clock source Select bit 0 With SCD = "0" the bits SCS1 and SCS0 are insignificant Table 23-4. SCS1 1 1 0 0 Serial Clock Source Select Bits SCS0 1 0 1 0 Internal Clock for SSI SYSCL/2 T1OUT/2 POUT/2 TOG2/2 * In transmit mode (SDD = 1) shifting starts only if the transmit buffer has been loaded (SRDY = 1). * Setting SIR bit loads the contents of the shift register into the receive buffer (synchronous 8-bit mode only). * In MCL modes, writing a 0 to SIR generates a start condition and writing a 1 generates a stop condition. 80 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 23.9.2 Serial Interface Control Register 2 (SIC2) Auxiliary register address: "A"hex Bit 3 MSM Bit 2 SM1 Bit 1 SM0 Bit 0 SDD Reset value: 1111b MSM Modular Stop Mode MSM = 1, modulator stop mode disabled (output masking off) MSM = 0, modulator stop mode enabled (output masking on) - used in modulation modes for generating bit streams which are not sub-multiples of 8 bits. Serial Mode control bit 1 Serial Mode control bit 0 SM1 SM0 Table 23-5. Mode 1 2 3 4 1 1 0 0 Serial Mode Control Bits SM0 1 0 1 0 SSI Mode 8-bit NRZ-Data changes with the rising edge of SC 8-bit NRZ-Data changes with the falling edge of SC 9-bit two-wire MCL mode 8-bit two-wire MCL mode (no acknowledge) SM1 SDD Serial Data Direction SDD = 1, transmit mode - SD line used as output (transmit data). SRDY is set ...... ...... by a transmit buffer write access. SDD = 0, receive mode - . SD line used as input (receive data). SRDY is set ...... ...... by a receive buffer read access SDD controls port directional control and defines the reset function for the SRDY flag Note: 81 4552H-4BMCU-07/07 23.9.3 Serial Interface Status and Control Register (SISC) Primary register address: "A"hex Bit 3 Write Read MCL --Bit 2 RACK TACK Bit 1 SIM ACT Bit 0 IFN SRDY Reset value: 1111b Reset value: xxxxb MCL Multi-Chip Link activation MCL = 1,multi-chip link disabled. This bit has to be set to "0" during transactions to/from EEPROM MCL = 0, connects SC and SD additionally to the internal multi-chip link pads Receive ACKnowledge status/control bit for MCL mode RACK = 0, transmit acknowledge in next receive telegram RACK = 1, transmit no acknowledge in last receive telegram Transmit ACKnowledge status/control bit for MCL mode TACK = 0, acknowledge received in last transmit telegram TACK = 1, no acknowledge received in last transmit telegram Serial Interrupt Mask SIM = 1, disable interrupts SIM = 0, enable serial interrupt. An interrupt is generated. Interrupt FuNction IFN = 1, the serial interrupt is generated at the end of telegram IFN = 0, the serial interrupt is generated when the SRDY goes low (i.e., buffer becomes empty/full in transmit/receive mode) Serial interface buffer ReaDY status flag SRDY = 1, in receive mode: receive buffer empty in transmit mode: transmit buffer full SRDY = 0, in receive mode: receive buffer full in transmit mode: transmit buffer empty Transmission ACTive status flag ACT = 1, transmission is active, i.e., serial data transfer. Stop or start conditions are currently in progress. ACT = 0, transmission is inactive RACK TACK SIM IFN SRDY ACT 23.9.4 Serial Transmit Buffer (STB) - Byte Write Primary register address: "9"hex First write cycle Second write cycle Bit 3 Bit 7 Bit 2 Bit 6 Bit 1 Bit 5 Bit 0 Bit 4 Reset value: xxxxb Reset value: xxxxb The STB is the transmit buffer of the SSI. The SSI transfers the transmit buffer into the shift register and starts shifting with the most significant bit. 82 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 23.9.5 Serial Receive Buffer (SRB) - Byte Read Primary register address: "9"hex First read cycle Second read cycle Bit 7 Bit 3 Bit 6 Bit 2 Bit 5 Bit 1 Bit 4 Bit 0 Reset value: xxxxb Reset value: xxxxb The SRB is the receive buffer of the SSI. The shift register clocks serial data in (most significant bit first) and loads content into the receive buffer when complete telegram has been received. 24. Combination Modes The UTCM consists of two timers (Timer 2 and Timer 3) and a serial interface. There is a multitude of modes in which the timers and serial interface can work together. The 8-bit wide serial interface operates as shift register for modulation and demodulation. The modulator and demodulator units work together with the timers and shift the data bits into or out of the shift register. 24.1 Combination Mode Timer 2 and SSI Figure 24-1. Combination Timer 2 and SSI I/O-bus P4CR T2I T2M1 T2M2 DCGO SYSCL T1OUT TOG3 SCL CL2/1 4-bit counter 2/1 RES OVF1 POUT CL2/2 T2O DCG 8-bit counter 2/2 RES OVF2 TOG2 Output T2C Compare 2/1 Timer 2 - control POUT CM1 Compare 2/2 INT4 MOUT Biphase-, Manchestermodulator T2CO1 TOG2 T2CM T2CO2 SO Timer 2 modulator output-stage Control I/O-bus SIC1 TOG2 POUT T1OUT SYSCL SCLI SIC2 SISC Control INT3 SO SC SSI-control MCL_SC Output SO SCL 8-bit shift register Shift_CL MSB LSB SI MCL_SD SD STB Transmit buffer I/O-bus SRB Receive buffer 83 4552H-4BMCU-07/07 24.1.1 Combination Mode 1: Burst Modulation SSI mode 1: Timer 2 mode 1, 2, 3 or 4: Timer 2 output mode 3: 8-bit NRZ and internal data SO output to the Timer 2 modulator stage 8-bit compare counter with 4-bit programmable prescaler and DCG Duty cycle burst generator Figure 24-2. Carrier Frequency Burst Modulation with the SSI Internal Data Output DCGO 1201201201201201201201201201201201201201 Counter 2 TOG2 SO T2O Bit 0 Bit 1 Bit 2 Counter = compare register (=2) Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 24.1.2 Combination Mode 2: Biphase Modulation 1 SSI mode 1: 8-bit shift register internal data output (SO) to the Timer 2 modulator stage Timer 2 mode 1, 2, 3 or 4: Timer 2 output mode 4: 8-bit compare counter with 4-bit programmable prescaler The modulator 2 of Timer 2 modulates the SSI internal data output to Biphase code Figure 24-3. Biphase Modulation 1 TOG2 SC 8-bit SR-data SO T2O 0 Bit 7 0 Data: 00110101 0 1 1 0 1 0 1 Bit 0 0 1 1 0 1 0 1 84 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 24.1.3 Combination Mode 3: Manchester Modulation 1 SSI mode 1: 8-bit shift register internal data output (SO) to the Timer 2 modulator stage Timer 2 mode 1, 2, 3 or 4: Timer 2 output mode 5: 8-bit compare counter with 4-bit programmable prescaler The modulator 2 of Timer 2 modulates the SSI internal data output to Manchester code Figure 24-4. Manchester Modulation 1 TOG2 SC 8-bit SR-data SO T2O 0 0 Bit 7 0 0 1 1 0 1 0 1 Bit 0 1 1 0 1 0 1 Bit 0 Bit 7 Data: 00110101 24.1.4 Combination Mode 4: Manchester Modulation 2 SSI mode 1: 8-bit shift register internal data output (SO) to the Timer 2 modulator stage Timer 2 mode 3: Timer 2 output mode 5: 8-bit compare counter and 4-bit prescaler The modulator 2 of Timer 2 modulates the SSI data output to Manchester code The 4-bit stage can be used as prescaler for the SSI to generate the stop signal for modulator 2. The SSI has a special mode to supply the prescaler with the shift clock. The control output signal (OMSK) of the SSI is used as stop signal for the modulator. Figure 24-5 shows an example for a 12-bit Manchester telegram. Figure 24-5. Manchester Modulation 2 SCLI Buffer full SIR SO SC MSM Timer 2 Mode 3 SCL Counter 2/1 OMSK T2O 0 0 0 0 0 Counter 2/1 = Compare Register 2/1 (= 4) 0 0 0 0 1 2 3 4 0 1 2 3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 85 4552H-4BMCU-07/07 24.1.5 Combination Mode 5: Biphase Modulation 2 SSI mode 1: 8-bit shift register internal data output (SO) to the Timer 2 modulator stage Timer 2 mode 3: Timer 2 output mode 4: 8-bit compare counter and 4-bit prescaler The modulator 2 of Timer 2 modulates the SSI data output to Biphase code The 4-bit stage can be used as prescaler for the SSI to generate the stop signal for modulator 2. The SSI has a special mode to supply the prescaler via the shift clock. The control output signal (OMSK) of the SSI is used as stop signal for the modulator. Figure 24-6 shows an example for a 13-bit Biphase telegram. Figure 24-6. Biphase Modulation SCLI Buffer full SIR SO SC MSM Timer 2 Mode 3 SCL Counter 2/1 OMSK T2O 0 0 0 0 0 Counter 2/1 = Compare Register 2/1 (= 5) 0 0 0 0 1 2 3 4 5 0 1 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 86 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 24.2 Combination Mode Timer 3 and SSI Figure 24-7. Combination Timer 3 and SSI I/O-bus T3CS T3I T3M T3EX T3I T3CP T3EX SYSCL T1OUT POUT CL3 RES Compare 3/1 Compare 3/2 Timer 3 - control CP3 CM31 RES T3C T3ST INT5 TOG3 SO Control M2 T3O Modulator 3 Demodulator 3 SC SI 8-bit counter 3 T3CO1 T3CO2 T3CM1 T3CM2 SI SC SIC1 TOG2 POUT T1OUT SYSCL SIC2 SISC Control INT3 SC MCL_SC Output SCLI SSI-control SO MSB 8-bit shift register SI LSB MCL_SD SI Shift_CL STB Transmit buffer I/O-bus SRB Receive buffer 87 4552H-4BMCU-07/07 24.2.1 Combination Mode 6: FSK Modulation SSI mode 1: 8-bit shift register internal data output (SO) to the Timer 3 Timer 3 mode 8: FSK modulation with shift register data (SO) The two compare registers are used to generate two varied time intervals. The SSI data output selects which compare register is used for the output frequency generation. A "0" level at the SSI data output enables the compare register 1 and a "1" level enables the compare register 2. The compare and compare mode registers must be programmed to generate the two frequencies via the output toggle flip-lop. The SSI can be supplied with the toggle signal of Timer 2 or any other clock source. The Timer 3 counter is driven by an internal or external clock source. Figure 24-8. FSK Modulation T3R 012340123401201201201201201201201201234012340 Counter 3 CM31 CM32 SO T3O 0 1 0 24.2.2 Combination Mode 7: Pulse-width Modulation (PWM) SSI mode 1: 8-bit shift register internal data output (SO) to the Timer 3 Timer 3 mode 9: Pulse-width modulation with the shift register data (SO) The two compare registers are used to generate two varied time intervals. The SSI data output selects which compare register is used for the output pulse generation. In this mode, both compare and compare mode registers must be programmed to generate the two pulse width. It is also useful to enable the single-action mode for extreme duty cycles. Timer 2 is used as baudrate generator and for the triggered restart of Timer 3. The SSI must be supplied with the toggle signal of Timer 2. The counter is driven by an internal or external clock source. Figure 24-9. Pulse-width Modulation TOG2 SIR 0 1 0 1 SO SCO T3R Counter 3 CM31 CM32 T3O 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 1011121314150 1 2 3 4 5 6 7 8 9 101112131415 0 1 2 3 4 88 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 24.2.3 Combination Mode 8: Manchester Demodulation/ Pulse-width Demodulation SSI mode 1: 8-bit shift register internal data input (SI) and the internal shift clock (SCI) from the Timer 3 Timer 3 mode 10: Manchester demodulation/pulse-width demodulation with Timer 3 For Manchester demodulation, the edge detection stage must be programmed to detect each edge at the input. These edges are evaluated by the demodulator stage. The timer stage is used to generate the shift clock for the SSI. A compare register 1 match event defines the correct moment for shifting the state from the input T3I as the decoded bit into shift register. After that, the demodulator waits for the next edge to synchronize the timer by a reset for the next bit. The compare register 2 can be used to detect a time error and handle it with an interrupt routine. Before activating the demodulator mode the timer and the demodulator stage must be synchronized with the bitstream. The Manchester code timing consists of parts with the half bitlength and the complete bitlength. A synchronization routine must start the demodulator after an interval with the complete bitlength. The counter can be driven by any internal clock source. The output T3O can be used by Timer 2 in this mode. The Manchester decoder can also be used for pulse-width demodulation. The input must programmed to detect the positive edge. The demodulator and timer must be synchronized with the leading edge of the pulse. After that a counter match with the compare register 1 shifts the state at the input T3I into the shift register. The next positive edge at the input restarts the timer. Figure 24-10. Manchester Demodulation Timer 3 mode T3I T3EX SI CM31=SCI SR-DATA 1 Bit 7 1 Bit 6 1 Bit 5 0 Bit 4 0 Bit 3 1 Bit 2 1 Bit 1 0 Bit 0 Synchronize 1 0 1 1 Manchester demodulation mode 1 0 0 1 1 0 89 4552H-4BMCU-07/07 24.2.4 Combination Mode 9: Biphase Demodulation SSI mode 1: 8-bit shift register internal data input (SI) and the internal shift clock (SCI) from the Timer 3 Timer 3 mode 11: Biphase demodulation with Timer 3 In the Biphase demodulation mode the timer works like in the Manchester demodulation mode. The difference is that the bits are decoded with the toggle flip-flop. This flip-flop samples the edge in the middle of the bitframe and the compare register 1 match event shifts the toggle flip-flop output into shift register. Before activating the demodulation the timer and the demodulation stage must be synchronized with the bitstream. The Biphase code timing consists of parts with the half bitlength and the complete bitlength. The synchronization routine must start the demodulator after an interval with the complete bitlength. The counter can be driven by any internal clock source and the output T3O can be used by Timer 2 in this mode. Figure 24-11. Biphase Demodulation Timer 3 mode T3I T3EX Q1=SI CM31=SCI Reset Counter 3 SR-DATA 0 Bit 7 1 Bit 6 1 Bit 5 0 Bit 4 1 Bit 3 0 Bit 2 1 Bit 1 0 Bit 0 Synchronize 0 0 1 1 Biphase demodulation mode 0 1 0 1 0 90 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 24.3 Combination Mode Timer 2 and Timer 3 Figure 24-12. Combination Timer 2 and Timer 3 I/O-bus T3CS T3I T3M T3EX T3I T3CP T3EX SYSCL T1OUT POUT CL3 SCI Demodulator 3 SI CP3 CM31 RES T3C T3ST INT5 TOG3 SO Control 8-bit counter 3 RES Compare 3/1 Compare 3/2 Timer 3 - control TOG2 T3CO1 T3CO2 T3CM1 T3CM2 I/O-bus T3O Modulator 3 M2 SSI T2I P4CR T2M1 DCGO T2M2 TOG3 SYSCL T1OUT SCL T2O CL2/1 4-bit counter 2/1 RES OVF1 CL2/2 POUT DCG 8-bit counter 2/2 RES OVF2 TOG2 OUTPUT MOUT M2 INT4 Biphase-, Manchestermodulator SO T2C Compare 2/1 CM1 Timer 2 - control POUT Compare 2/2 T2CO1 I/O-bus SSI T2CM T2CO2 Timer 2 modulator 2 output-stage SSI Control (RE, FE, SCO, OMSK) 24.3.1 Combination Mode 10: Frequency Measurement or Event Counter with Time Gate Timer 2 mode 1/2: 12-bit compare counter/8-bit compare counter and 4-bit prescaler Timer 2 output mode 1/6: Timer 3 mode 3: Timer 2 compare match toggles (TOG2) to the Timer 3 Timer/Counter; internal trigger restart and internal capture (with Timer 2 TOG2-signal) The counter is driven by an external (T3I) clock source. The output signal (TOG2) of Timer 2 resets the counter. The counter value before reset is saved in the capture register. If single-action mode is activated for one or both compare registers, the trigger signal restarts also the single actions. This mode can be used for frequency measurements or as event counter with time gate. 91 4552H-4BMCU-07/07 Figure 24-13. Frequency Measurement T3R T3I Counter 3 0 0 1 2 3 4 5 6 7 8 9 1011121314151617 0 1 2 3 4 5 6 7 8 9 101112131415161718 0 1 2 3 4 5 TOG2 T3CPRegister Capture value = 0 Capture value = 17 Capt. value = 18 Figure 24-14. Event Counter with Time Gate T3R T3I Counter 3 TOG2 T3CPRegister Capture value = 0 Capture value = 11 Cap. val. = 4 0 0 1 2 3 4 5 6 7 8 9 10 11 01 2 3 4 012 24.3.2 Combination Mode 11: Burst Modulation 1 Timer 2 mode 1/2: 12-bit compare counter/8-bit compare counter and 4-bit prescaler Timer 2 output mode 1/6: Timer 3 mode 6: Timer 2 compare match toggles the output flip-flop (M2) to the Timer 3 Carrier frequency burst modulation controlled by Timer 2 output (M2) The Timer 3 counter is driven by an internal or external clock source. Its compare and compare mode registers must be programmed to generate the carrier frequency with the output toggle flip-flop. The output toggle flip-flop (M2) of Timer 2 is used to enable and disable the Timer 3 output. The Timer 2 can be driven by the toggle output signal of Timer 3 (TOG3) or any other clock source. Figure 24-15. Burst Modulation 1 CL3 Counter 3 CM1 CM2 TOG3 M3 Counter 2/2 TOG2 M2 T3O 3 0 1 2 3 3 0 1 2 3 0 1 01 2 34 5 01 0 12 3 4 5 0 10 1 23 4 50 1 01 5 0 1 01 50 1 01 501 01 5 01 01 501 01 5 01 01 5 01 01 5 01 01 5 01 01 92 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 24.4 Combination Mode Timer 2, Timer 3 and SSI Figure 24-16. Combination Timer 2, Timer 3 and SSI I/O-bus T3CS T3I T3M T3EX T3I T3CP T3EX SYSCL T1OUT POUT CP3 CM31 RES CL3 SCI Demodulator 3 SI 8-bit Counter 3 T3C T3ST INT5 TOG3 SO Control RES Compare 3/1 Compare 3/2 T3O Modulator 3 Timer 3 - control M2 TOG2 T3CO1 T3CO2 T3CM1 T3CM2 I/O-bus SSI P4CR T2I T2M1 DCGO T2M2 TOG3 SYSCL T1OUT SCL T2C T2O CL2/1 4-bit Counter 2/1 RES OVF1 CL2/2 POUT DCG 8-bit Counter 2/2 RES OVF2 TOG2 OUTPUT MOUT M2 Compare 2/1 CM1 T2CO1 Timer 2 - control POUT T2CM Compare 2/2 INT4 T2CO2 SO Control Biphase-, Manchestermodulator I/O-bus SIC1 TOG2 Control SIC2 SISC (RE, FE, SCO, OMSK) Timer 2 modulator 2 output-stage INT3 SCLI SC MCL_SC POUT T1OUT SYSCL SSI-control SO Output SI Shift_CL MSB SCL MCL_SD SI 8-bit shift register LSB STB Transmit buffer I/O-bus SRB Receive buffer 93 4552H-4BMCU-07/07 24.4.1 Combination Mode 12: Burst Modulation 2 SSI mode 1: 8-bit shift register internal data output (SO) to the Timer 3 Timer 2 output mode 2: Timer 2 output mode 1/6: Timer 3 mode 7: 8-bit compare counter and 4-bit prescaler Timer 2 compare match toggles (TOG2) to the SSI Carrier frequency burst modulation controlled by the internal output (SO) of SSI The Timer 3 counter is driven by an internal or external clock source. Its compare and compare mode registers must be programmed to generate the carrier frequency with the output toggle flip-flop (M3). The internal data output (SO) of the SSI is used to enable and disable the Timer 3 output. The SSI can be supplied with the toggle signal of Timer 2. Figure 24-17. Burst Modulation 2 CL3 Counter 3 CM31 CM32 TOG3 M3 Counter 2/2 TOG2 SO T3O 3 0 1 2 3 3 0 1 2 3 0 1 01 2 34 5 01 0 12 3 45 0 10 1 23 4 50 1 01 5 0 1 01 5 0 1 01 5 01 01 5 0 1 01 501 01 5 01 01 501 01 501 01 5 0 1 01 24.4.2 Combination Mode 13: FSK Modulation SSI mode 1: Timer 2 output mode 3: Timer 2 output mode 1/6: Timer 3 mode 8: 8-bit shift register internal data output (SO) to the Timer 3 8-bit compare counter and 4-bit prescaler Timer 2 4-bit compare match signal (POUT) to the SSI FSK modulation with shift register data output (SO) The two compare registers are used to generate two different time intervals. The SSI data output selects which compare register is used for the output frequency generation. A "0" level at the SSI data output enables the compare register 1 and a "1" level enables the compare register 2. The compare- and compare mode registers must be programmed to generate the two frequencies via the output toggle flip-flop. The SSI can be supplied with the toggle signal of Timer 2 or any other clock source. The Timer 3 counter is driven by an internal or external clock source. 94 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 Figure 24-18. FSK Modulation T3R 0123401234012340120120120120120120120123401 Counter 3 CM31 CM32 SO T3O 0 1 0 24.5 Microcontroller Block The microcontroller block is a multichip device which offers a combination of a MARC4-based microcontroller and a serial E2PROM data memory in a single package. A microcontroller is used and as serial E2PROM the U505M. Two internal lines can be used as chip-to-chip link in a single package. The maximum internal data communication frequency between the microcontroller block and the U505M over the chip link (MCL_SC and MCL_SD) is fSC_MCL = 500 kHz. The microcontroller and the EEPROM portions of this multi-chip device are equivalent to their respective individual component chips, except for the electrical specification. 24.5.1 Internal 2-wire Multi-chip Link Two additional on-chip pads (MCL_SC and MCL_SD) for the SC and the SD line can be used as chip-to-chip link for multi-chip applications. These pads can be activated by setting the MCL bit in the SISC register. Figure 24-19. Link between the Microcontroller Block and U505M U505M SCL SDA Multi chip link MCL_SC V DD BP40/SC MCL_SD V SS BP43/SD Microcontroller BP10 BP13 95 4552H-4BMCU-07/07 24.6 U505M EEPROM The U505M is a 512-bit EEPROM internally organized as 32 x 16-bits. The programming voltage as well as the write-cycle timing is generated on-chip. The U505M features a serial interface allowing operation on a simple two-wire bus with an MCL protocol. Its low power consumption makes it well suited for battery applications. Figure 24-20. Block Diagram EEPROM Timing control HV-generator V DD V SS Address control EEPROM 32 x 16 Mode control 16-bit read/write buffer SCL I/O control SDA 8-bit data register 96 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 24.7 Serial Interface The U505M has a two-wire serial interface (TWI) to the microcontroller for read and write accesses to the EEPROM. The U505M is considered to be a slave in all these applications. That means, the controller has to be the master that initiates the data transfer and provides the clock for transmit and receive operations. The serial interface is controlled by the microcontroller block which generates the serial clock and controls the access via the SCL line and SDA line. SCL is used to clock the data into and out of the device. SDA is a bi-directional line that is used to transfer data into and out of the device. The following protocol is used for the data transfers. 24.7.1 Serial Protocol * Data states on the SDA line changing only while SCL is low. * Changes on the SDA line while SCL is high are interpreted as START or STOP condition. * A START condition is defined as high to low transition on the SDA line while the SCL-line is high. * A STOP condition is defined as low to high transition on the SDA line while the SCL line is high. * Each data transfer must be initialized with a START condition and terminated with a STOP condition. The START condition wakes the device from standby mode and the STOP condition returns the device to standby mode. * A receiving device generates an acknowledge (A) after the reception of each byte. This requires an additional clock pulse, generated by the master. If the reception was successful the receiving master or slave device pulls down the SDA line during that clock cycle. If an acknowledge is not detected (N) by the interface in transmit mode, it will terminate further data transmissions and go into receive mode. A master device must finish its read operation by a non-acknowledge and then send a stop condition to bring the device into a known state. Figure 24-21. MCL Protocol SCL SDA Stand Start by condition Data valid Data/ Data change acknowledge valid Stop Standcondition by * Before the START condition and after the STOP condition the device is in standby mode and the SDA line is switched as input with pull-up resistor. * The control byte that follows the START condition determines the following operation. It consists of the 5-bit row address, 2 mode control bits and the READ/NWRITE bit that is used to control the direction of the following transfer. A "0" defines a write access and a "1" a read access. 97 4552H-4BMCU-07/07 24.7.2 Control Byte Format EEPROM Address Start A4 A3 A2 A1 A0 Mode Control Bits C1 C0 Read/ NWrite R/NW Ackn Start Control byte Ackn Data byte Ackn Data byte Ackn Stop 24.8 EEPROM The EEPROM has a size of 512 bits and is organized as 32 x 16-bit matrix. To read and write data to and from the EEPROM the serial interface must be used. The interface supports one and two byte write accesses and one to n-byte read accesses to the EEPROM. 24.8.1 EEPROM - Operating Modes The operating modes of the EEPROM are defined via the control byte. The control byte contains the row address, the mode control bits and the read/not-write bit that is used to control the direction of the following transfer. A "0" defines a write access and a "1" a read access. The five address bits select one of the 32 rows of the EEPROM memory to be accessed. For all accesses the complete 16-bit word of the selected row is loaded into a buffer. The buffer must be read or overwritten via the serial interface. The two mode control bits C1 and C2 define in which order the accesses to the buffer are performed: High byte - low byte or low byte - high byte. The EEPROM also supports autoincrement and autodecrement read operations. After sending the start address with the corresponding mode, consecutive memory cells can be read row by row without transmission of the row addresses. Two special control bytes enable the complete initialization of EEPROM with "0" or with "1". 24.8.2 Write Operations The EEPROM permits 8-bit and 16-bit write operations. A write access starts with the START condition followed by a write control byte and one or two data bytes from the master. It is completed via the STOP condition from the master after the acknowledge cycle. The programming cycle consists of an erase cycle (write "zeros") and the write cycle (write "ones"). Both cycles together take about 10 ms. 24.8.3 Acknowledge Polling If the EEPROM is busy with an internal write cycle, all inputs are disabled and the EEPROM will not acknowledge until the write cycle is finished. This can be used to detect the end of the write cycle. The master must perform acknowledge polling by sending a start condition followed by the control byte. If the device is still busy with the write cycle, it will not return an acknowledge and the master has to generate a stop condition or perform further acknowledge polling sequences. If the cycle is complete, it returns an acknowledge and the master can proceed with the next read or write cycle. 98 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 24.8.4 Write One Data Byte Start Control byte A Data byte 1 A Stop 24.8.5 Write Two Data Bytes Start Control byte A Data byte 1 A Data byte 2 A Stop 24.8.6 Write Control Byte Only Start Control byte A Stop 24.8.7 Write Control Bytes MSB Write low byte first A4 A3 A2 A1 A0 C1 0 C0 1 LSB R/NW 0 Row address Byte order LB(R) HB(R) MSB Write high byte first A4 A3 A2 A1 A0 C1 1 C0 0 LSB R/NW 0 Row address Byte order HB(R) LB(R) A -> acknowledge; HB -> high byte; LB -> low byte; R -> row address 24.8.8 Read Operations The EEPROM allows byte-, word- and current address read operations. The read operations are initiated in the same way as write operations. Every read access is initiated by sending the START condition followed by the control byte which contains the address and the read mode. When the device has received a read command, it returns an acknowledge, loads the addressed word into the read/write buffer and sends the selected data byte to the master. The master has to acknowledge the received byte if it wants to proceed the read operation. If two bytes are read out from the buffer the device increments respectively decrements the word address automatically and loads the buffer with the next word. The read mode bits determines if the low or high byte is read first from the buffer and if the word address is incremented or decremented for the next read access. If the memory address limit is reached, the data word address will roll over and the sequential read will continue. The master can terminate the read operation after every byte by not responding with an acknowledge (N) and by issuing a stop condition. 99 4552H-4BMCU-07/07 24.8.9 Read One Data Byte Start Control byte A Data byte 1 N Stop 24.8.10 Read Two Data Bytes Start Control byte A Data byte 1 A Data byte 2 N Stop 24.8.11 Read n Data Bytes Start Control byte A Data byte 1 A Data byte 2 A - Data byte n N Stop 24.8.12 Read Control Bytes MSB Read low byte first, address increment A4 A3 A2 A1 A0 C1 0 C0 1 LSB R/NW 1 Row address Byte order LB(R) HB(R) LB(R+1) HB(R+1) --- LB(R+n) HB(R+n) MSB Read high byte first, address decrement A4 A3 A2 A1 A0 C1 1 C0 0 LSB R/NW 1 Row address Byte order HB(R) LB(R) HB(R-1) LB(R-1) --- HB(R-n) LB(R-n) A -> acknowledge, N -> no acknowledge; HB -> high byte; LB -> low byte, R -> row address 24.9 Initialization After a Reset Condition The EEPROM with the serial interface has its own reset circuitry. In systems with microcontrollers that have their own reset circuitry for power-on reset, watchdog reset or brown-out reset, it may be necessary to bring the U505M into a known state independent of its internal reset. This is performed by writing: Start Control byte A Data byte 1 N Stop to the serial interface. If the U505M acknowledges this sequence it is in a defined state. Maybe it is necessary to perform this sequence twice. 100 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 25. Absolute Maximum Ratings: Microcontroller Part Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All inputs and outputs are protected against high electrostatic voltages or electric fields. However, precautions to minimize the build-up of electrostatic charges during handling are recommended. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g., VDD). Voltages are given relative to VSS Parameters Supply voltage Input voltage (on any pin) Output short circuit duration Operating temperature range Storage temperature range Soldering temperature (t 10s) Symbol VDD VIN tshort Tamb Tstg Tsld Value -0.3 to +4.0 VSS -0.3 VIN VDD +0.3 Indefinite -40 to +125 -40 to +130 260 Unit V V s C C C 26. Thermal Resistance Parameter Thermal resistance Symbol RthJA Value 135 Unit K/W 27. DC Operating Characteristics VSS = 0V, Tamb = -40C to +125C unless otherwise specified. Parameters Power Supply Operating voltage at VDD Active current CPU active Power down current (CPU sleep, RC oscillator active, 4-MHz quartz oscillator active) Sleep current (CPU sleep, 32-kHz quartz oscillator active 4-MHz quartz oscillator inactive) Sleep current (CPU sleep, 32-kHz quartz oscillator inactive 4-MHz quartz oscillator inactive) Pin capacitance Power-on Reset Threshold Voltage POR threshold voltage POR threshold voltage POR hysteresis BOT = 1 BOT = 0 VPOR VPOR VPOR 1.6 1.85 1.7 2.0 50 1.8 2.15 V V mV fSYSCL = 1 MHz VDD = 1.8V VDD = 3.0V fSYSCL = 1 MHz VDD = 1.8V VDD = 3.0V VDD = 1.8V VDD = 3.0V VDD = 1.8V VDD = 3.0V Any pin to VSS VDD IDD VPOR 200 300 40 70 0.4 0.6 0.1 0.3 7 4.0 V A A A A A A A A pF Test Conditions Symbol Min. Typ. Max. Unit 450 IPD 180 ISleep 2.3 ISleep CL 1.5 10 101 4552H-4BMCU-07/07 27. DC Operating Characteristics (Continued) VSS = 0V, Tamb = -40C to +125C unless otherwise specified. Parameters Voltage Monitor Threshold Voltage VM high threshold voltage VM high threshold voltage VM middle threshold voltage VM middle threshold voltage VM low threshold voltage VM low threshold voltage External Input Voltage VMI VMI All Bi-directional Ports Input voltage LOW Input voltage HIGH Input LOW current (switched pull-up) Input HIGH current (switched pull-down) Input LOW current (static pull-up) Input LOW current (static pull-down) Input leakage current Input leakage current Output LOW current VDD = 1.8 to 6.5V VDD = 1.8 to 6.5V VDD = 2.0V, VDD = 3.0V, VIL= VSS VDD = 2.0V, VDD = 3.0V, VIH = VDD VDD = 2.0V VDD = 3.0V, VIL= VSS VDD = 2.0V VDD = 3.0V, VIH= VDD VIL= VSS VIH= VDD VOL = 0.2 x VDD VDD = 2.0V VDD = 3.0V VOH = 0.8 x VDD VDD = 2.0V VDD = 3.0V VIL VIH IIL IIH IIL IIH IIL IIH IOL 0.5 2 -0.5 -2 1.2 5 -1.2 -5 VSS 0.8 x VDD -1.4 -7 1.4 7 -14 --60 14 60 -4 -20 4 20 -50 -160 50 160 0.2 x VDD VDD -12 -40 12 40 -100 -320 100 320 100 100 2.5 8 -2.5 -8 V V A A A A A A A A nA nA mA mA mA mA VDD = 3V, VMS = 1 VDD = 3V, VMS = 0 VVMI VVMI 1.2 1.3 1.3 1.4 V V VDD > VM, VMS = 1 VDD < VM, VMS = 0 VDD > VM, VMS = 1 VDD < VM, VMS = 0 VDD > VM, VMS = 1 VDD < VM, VMS = 0 VMThh VMThh VMThm VMThm VMThl VMThl 1.97 2.36 2.75 3.0 3.0 2.6 2.6 2.2 2.2 2.4 2.8 3.25 V V V V V V Test Conditions Symbol Min. Typ. Max. Unit Output HIGH current Note: IOH The pin BP20/NTE has a static pull-up resistor during the reset-phase of the microcontroller. 102 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 28. AC Characteristics Supply Voltage VDD = 1.8V to 4.0V, VSS = 0V, Tamb = 25C unless otherwise specified. Parameters Operation Cycle Time VDD = 1.8V to 4.0V Tamb = -40C to +125C VDD = 2.4V to 4.0V Tamb = -40C to +125C tSYSCL tSYSCL 500 250 4000 4000 ns ns Test Conditions Symbol Min. Typ. Max. Unit System clock cycle Timer 2 input Timing Pin T2I Timer 2 input clock Timer 2 input LOW time Timer 2 input HIGH time Timer 3 Input Timing Pin T3I Timer 3 input clock Timer 3 input LOW time Timer 3 input HIGH time Interrupt Request Input Timing Interrupt request LOW time Interrupt request HIGH time External System Clock EXSCL at OSC1, ECM = EN EXSCL at OSC1, ECM = DI Input HIGH time Reset Timing Power-on reset time RC Oscillator 1 Frequency Stability RC Oscillator 2 - External Resistor Frequency Stability Stabilization time 4-MHz Crystal Oscillator (Operating Range VDD = 2.2V to 4.0V) Frequency Start-up time Stability Integrated input/output capacitances (mask programmable) CIN/COUT programmable in steps of 2 pF fX tSQ f/f CIN COUT -10 0 0 4 5 10 20 20 MHz ms ppm pF pF Rext = 170 k VDD = 2.0V to 4.0V Tamb = -40C to +105C fRcOut2 f/f tS 4 15 10 MHz % s VDD = 2.0V to 4.0V Tamb = -40C to +105C fRcOut1 f/f 3.8 50 MHz % VDD > VPOR tPOR 1.5 5 ms Rise/fall time < 10 ns Rise/fall time < 10 ns Rise/fall time < 10 ns fEXSCL fEXSCL tIH 0.5 0.02 0.1 4 4 MHz MHz s Rise/fall time < 10 ns Rise/fall time < 10 ns tIRL tIRH 100 100 ns ns Rise/fall time < 10 ns Rise/fall time < 10 ns fT3I tT3IL tT3IH 2 tSYSCL 2 tSYSCL SYSCL/2 MHz ns ns Rise/fall time < 10 ns Rise/fall time < 10 ns fT2I tT2IL tT2IH 100 100 5 MHz ns ns 103 4552H-4BMCU-07/07 28. AC Characteristics (Continued) Supply Voltage VDD = 1.8V to 4.0V, VSS = 0V, Tamb = 25C unless otherwise specified. Parameters Frequency Start-up time Stability Integrated input/output capacitances (mask programmable) External 32-kHz Crystal Parameters Crystal frequency Serial resistance Static capacitance Dynamic capacitance External 4-MHz Crystal Parameters Crystal frequency Serial resistance Static capacitance Dynamic capacitance EEPROM Operating current during erase/write cycle Endurance Data erase/write cycle time Data retention time Power-up to read operation Power-up to write operation Serial Interface SCL clock frequency fSC_MCL 100 500 kHz Erase-/write cycles ......Tamb = 105C For 16-bit access ......Tamb = 105C IWR ED ED tDEW tDR tDR tPUR tPUW 100 1 0.2 0.2 500000 50000 600 1000000 100000 9 12 1300 A Cycles Cycles ms Years Years ms ms fX RS C0 C1 4.0 40 1.4 3 150 3 MHz W pF fF fX RS C0 C1 32.768 30 1.5 3 50 kHz k pF fF CIN/COUT programmable in steps of 2 pF Test Conditions Symbol fX tSQ f/f CIN COUT -10 0 0 Min. Typ. 32.768 0.5 10 20 20 Max. Unit kHz s ppm pF pF 32-kHz Crystal Oscillator (Operating Range VDD = 2.0V to 4.0V) 29. Crystal Characteristics Figure 29-1. Crystal Equivalent Circuit L Equivalent circuit OSCIN SCLIN OSCOUT SCLOUT C1 RS C0 104 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 30. Emulation The basic function of emulation is to test and evaluate the customer's program and hardware in real time. This therefore enables the analysis of any timing, hardware or software problem. For emulation purposes, all MARC4 controllers include a special emulation mode. In this mode, the internal CPU core is inactive and the I/O buses are available via Port 0 and Port 1 to allow an external access to the on-chip peripherals. The MARC4 emulator uses this mode to control the peripherals of any MARC4 controller (target chip) and emulates the lost ports for the application. The MARC4 emulator can stop and restart a program at specified points during execution, making it possible for the applications engineer to view the memory contents and those of various registers during program execution. The designer also gains the ability to analyze the executed instruction sequences and all the I/O activities. Figure 30-1. MARC4 Emulation Emulator target board MARC4 emulator Program memory MARC4 emulation-CPU I/O bus MARC4 target chip Port 0 I/O control Port 1 Trace memory CORE CORE (inactive) Peripherals Port 0 Control logic Port 1 Emulation control SYSCL/ TCL, TE, NRST Application-specific hardware Personal computer 105 4552H-4BMCU-07/07 31. Option Settings for Ordering Please select the option settings from the list below and insert ROM CRC. Output(1) Input [] [X] [] [] [X] [] [] CMOS Open drain [N] Open drain [P] [] [X] [] [] [] [] [] BP21 Recommended settings for pins not available externally BP22 Recommended settings for pins not available externally BP23 [X] [] [] CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] [] [] [] [] [] [X] [] [] [X] [] [] CMOS Open drain [N] Open drain [P] [] [X] [] [] [] [] [] Port 4 BP40 [] [] [] CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] [] [] [] [] [] [] [] [] BP41 [] [] [] BP42 [] [] [] BP43 [] [] [] CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] [] [] [] [] [] [] [] [] [] [] [] [] Switched pull-up Switched pull-down Static pull-up Static pull-down Switched pull-up Switched pull-down Static pull-up Static pull-down Switched pull-up Switched pull-down Static pull-up Static pull-down Switched pull-up Switched pull-down Static pull-up Static pull-down Switched pull-up Switched pull-down Static pull-up Static pull-down Switched pull-up Switched pull-down Static pull-up Static pull-down Switched pull-up Switched pull-down Static pull-up Static pull-down Switched pull-up Switched pull-down Static pull-up Static pull-down Switched pull-up Switched pull-down Static pull-up Static pull-down Switched pull-up Switched pull-down Static pull-up Static pull-down ECM (External Clock Monitor) [] [] Enable Disable Clock Used [] [] [] [] [] External resistor External clock OSC1 or External clock OSC2 32-kHz crystal 4-MHz crystal OSC2 OSC1 [] [] [] [] No integrated capacitance Internal capacitance [ _____pF] (Cint = 0 to 20 pF in steps of 0.63 pF) No integrated capacitance Internal capacitance [ _____pF] (Cint = 0 to 20 pF in steps of 0.63 pF) BP63 [] [] [] CMOS Open drain [N] Open drain [P] Port 6 BP60 [] [] [] CMOS Open drain [N] Open drain [P] BP53 [] [] [] CMOS Open drain [N] Open drain [P] BP51 Recommended settings for pins not available externally BP52 [X] [] [] CMOS Open drain [N] Open drain [P] Port 5 BP50 [] [] [] Output CMOS Open drain [N] Open drain [P] [] [] [] [] [] [X] [] [] [] [] [] CMOS Open drain [N] Open drain [P] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] Input Switched pull-up Switched pull-down Static pull-up Static pull-down Switched pull-up Switched pull-down Static pull-up Static pull-down Switched pull-up Switched pull-down Static pull-up Static pull-down Switched pull-up Switched pull-down Static pull-up Static pull-down Switched pull-up Switched pull-down Static pull-up Static pull-down Switched pull-up Switched pull-down Static pull-up Static pull-down Port 1 BP10 [X] [] [] CMOS Open drain [N] Open drain [P] Recommended settings for pins not available externally(2) BP13 Recommended settings for pins not available externally(2) Port 2 BP20 (3) Approval: Note: File: Date: .HEX CRC: Signature: HEX 1. It is required to select an output option for each port pin (Port 1, Port 4, Port 5, Port 6) 2. It is required to select one of the input options for pons not available externally or to use the recommended settings. 3. Do not use external components at BP20 that pull to VSS during reset representing a resistor < 150 k. 106 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 32. Ordering Information Extended Type Number(1) ATAR862x-yyy-TNQYf Note: 1. x = yyy = TN = Q= Y= f = Program Memory 4 kB ROM Data-EEPROM 512 bit Package SSO24 Delivery Taped and reeled Hardware revision Customer specific ROM-version and customizing Package (SSO24) Taped and reeled (4000 pcs) Lead free RF operating frequency, 4 means 433 MHz, 3 and 8 or unless customized 33. Package Information 5.40.2 8.05-0.25 4.40.1 0.05+0.1 1.30.05 0.250.05 0.650.05 7.150.05 6.450.15 24 13 Package: SSO24 Dimensions in mm technical drawings according to DIN specifications 1 Drawing-No.: 6.543-5056.02-4 Issue: 1; 07.06.01 12 0.150.05 107 4552H-4BMCU-07/07 34. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4552H-4BMCU-07/07 History * Put datasheet in a new template * Features Maximum output power value and low current value on page 1 are changed * ESD protection of the "UHF ASK/FSK Transmitter Block" in section 3 on page 4 is transferred to the appropriate product PPAP * Table "Ordering Information" on page 107 changed * Put datasheet in new template * Page 30: Section "32-kHz Oscillator" changed * Page 107: Ordering Information changed * Abs. Max. Ratings table (page 11): row "Input voltage" changed * Abs. Max. Ratings table (page 11): table note 1 changed * El. Char. table (page 12): row "PA_ENABLE input" changed * El. Char. table (page 12): table note 1 changed 4552G-4BMCU-09/06 4552F-4BMCU-05/06 4552E-4BMCU-09/04 108 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 35. Table of Contents 1 2 3 4 5 6 7 Description .............................................................................................1 Pin Configuration ...................................................................................2 UHF ASK/FSK Transmitter Block .........................................................4 Features ..................................................................................................4 Description .............................................................................................4 General Description ...............................................................................6 Functional Description ..........................................................................6 7.1 7.2 7.3 7.4 ASK Transmission ..........................................................................................6 FSK Transmission ..........................................................................................6 CLK Output .....................................................................................................7 Application Circuit ...........................................................................................8 8 9 Absolute Maximum Ratings: RF Part .................................................11 Thermal Resistance .............................................................................11 10 Electrical Characteristics ....................................................................11 11 Microcontroller Block ..........................................................................13 12 Features ................................................................................................13 13 Description ...........................................................................................13 14 Introduction ..........................................................................................14 15 MARC4 Architecture General Description .........................................15 16 Components of MARC4 Core ..............................................................15 16.1 16.2 16.3 16.4 16.5 16.6 16.7 16.8 16.9 ROM .............................................................................................................16 RAM ..............................................................................................................16 Registers ......................................................................................................17 ALU ...............................................................................................................19 I/O Bus ..........................................................................................................19 Instruction Set ...............................................................................................19 Interrupt Structure .........................................................................................20 Software Interrupts .......................................................................................22 Hardware Interrupts ......................................................................................22 109 4552H-4BMCU-07/07 17 Master Reset .........................................................................................23 17.1 Power-on Reset and Brown-out Detection ...................................................23 18 Voltage Monitor ....................................................................................24 19 Clock Generation .................................................................................26 19.1 19.2 19.3 Clock Module ................................................................................................26 Oscillator Circuits and External Clock Input Stage .......................................27 Clock Management .......................................................................................30 20 Power-down Modes .............................................................................31 21 Peripheral Modules ..............................................................................32 21.1 21.2 21.3 21.4 21.5 21.6 21.7 21.8 21.9 21.10 21.11 21.12 21.13 21.14 Addressing Peripherals ................................................................................32 Bi-directional Ports .......................................................................................35 Bi-directional Port 1 ......................................................................................35 Bi-directional Port 2 ......................................................................................36 Bi-directional Port 5 ......................................................................................38 Bi-directional Port 4 ......................................................................................40 Bi-directional Port 6 ......................................................................................41 Universal Timer/Counter/ Communication Module (UTCM) .........................42 Timer 1 .........................................................................................................43 Timer 2 .........................................................................................................47 Timer 2 Modes ..............................................................................................48 Timer 2 Output Modes ..................................................................................50 Timer 2 Output Signals .................................................................................50 Timer 2 Registers .........................................................................................53 22 Timer 3 ..................................................................................................58 22.1 22.2 22.3 22.4 22.5 22.6 22.7 22.8 22.9 Features .......................................................................................................58 Timer/Counter Modes ...................................................................................59 Timer 3 Modulator/Demodulator Modes .......................................................63 Timer 3 Modulator for Carrier Frequency Burst Modulation .........................66 Timer 3 Demodulator for Biphase, Manchester and Pulse-width-modulated Signals ..........................................................................................................66 Timer 3 Registers ......................................................................................... 67 Timer 3 Capture Register .............................................................................71 Synchronous Serial Interface (SSI) ..............................................................72 Serial Interface Registers .............................................................................80 110 ATAR862-4 4552H-4BMCU-07/07 ATAR862-4 23 Combination Modes .............................................................................83 23.1 23.2 23.3 23.4 23.5 23.6 23.7 23.8 23.9 Combination Mode Timer 2 and SSI ............................................................83 Combination Mode Timer 3 and SSI ............................................................87 Combination Mode Timer 2 and Timer 3 ......................................................91 Combination Mode Timer 2, Timer 3 and SSI ..............................................93 Microcontroller Block ....................................................................................95 U505M EEPROM .........................................................................................96 Serial Interface .............................................................................................97 EEPROM ......................................................................................................98 Initialization After a Reset Condition ...........................................................100 24 Absolute Maximum Ratings: Microcontroller Part ..........................101 25 Thermal Resistance ...........................................................................101 26 DC Operating Characteristics ...........................................................101 27 AC Characteristics .............................................................................103 28 Crystal Characteristics ......................................................................104 29 Emulation ............................................................................................105 30 Option Settings for Ordering ...........................................................106 31 Ordering Information .........................................................................107 32 Package Information ..........................................................................107 33 Revision History .................................................................................108 34 Table of Contents ...............................................................................109 111 4552H-4BMCU-07/07 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-en-Yvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support marc4@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. (c) 2007 Atmel Corporation. All rights reserved. Atmel (R), logo and combinations thereof, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 4552H-4BMCU-07/07 |
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